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2.0 v, 32/16 kb flash, smartclock, 12-bit adc C8051F410/1/2/3 rev. 0.8 11/06 copyright ? 2006 by silicon laboratories c8051f41x this information applies to a product under development. its char acteristics and specifications are subject to change without n otice. analog peripherals - 12-bit adc ? 1 lsb inl; no missing codes programmable throughput up to 200 ksps up to 24 external inputs data dependent windowed interrupt generator built-in temperature sensor (3 c) - two 12-bit current mode dacs - two comparators programmable hysteresis and response time configurable as wake-up or reset source - por/brownout detector - voltage reference?1.5, 2.2 v (programmable) on-chip debug - on-chip debug circuitry facilitates full-speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping - inspect/modify memory and registers - complete development kit supply voltage 2.0 to 5.25 v - built-in ldo regulator: 2.1 or 2.5 v high speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 50 mips throughput with 50 mhz system clock - expanded interrupt handler memory - 2304 bytes internal data ram (256 + 2048) - 32/16 kb flash; in-system programmable in 512 byte sectors - 64 bytes battery-backed ram (smartclock) digital peripherals - 24 port i/o; push-pull or open-drain, up to 5.25 v tolerance - hardware smbus? (i2c? compatible), spi?, and uart serial ports available concurrently - four general purpose 16-bit counter/timers - programmable 16-bit counter/timer array with six capture/compare modules, wdt - hardware smartclock operates down to 1 v with 64 bytes battery-backed ram and backup voltage regulator clock sources - internal oscillators: 24.5 mhz 2% accuracy supports uart operation; clock multiplier up to 50 mhz - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - smartclock oscillator: 32 khz crystal or self-resonant oscillator - can switch between clock sources on-the-fly 32-pin lqfp or 28-pin 5x5 qfn temperature range: ?40 to +85 c analog peripherals 12-bit 200ksps adc 32/16 kb isp flash 2368 b sram por debug circuitry flexible interrupts 8051 cpu (50 mips) temp sensor digital i/o 24.5 mhz precision internal oscillator with clock multiplier high-speed controller core a m u x crossbar voltage comparators + - wdt uart smbus pca timer 0 timer 1 timer 2 timer 3 port 0 spi 12-bit idac port 1 12-bit idac port 2 + - vreg low frequency internal oscillator vref crc hardware smartclock
C8051F410/1/2/3 2 rev. 0.8 n otes :
rev. 0.8 3 C8051F410/1/2/3 table of contents 1. system overview.................................................................................................... 19 1.1. cip-51? microcontroller................................................................................... 25 1.1.1. fully 8051 compatible instruction set...................................................... 25 1.1.2. improved throughput ............................................................................... 25 1.1.3. additional features .................................................................................. 25 1.2. on-chip debug circuitry................................................................................... 26 1.3. on-chip memory............................................................................................... 27 1.4. operating modes .............................................................................................. 28 1.5. 12-bit analog to digital converter..................................................................... 29 1.6. two 12-bit current-mode dacs........................................................................ 29 1.7. programmable comparators............................................................................. 30 1.8. cyclic redundancy check unit......................................................................... 31 1.9. voltage regulator ............................................................................................. 31 1.10.serial ports ....................................................................................................... 31 1.11.smartclock (real time clock) ....................................................................... 32 1.12.port input/output .............................................................................................. 33 1.13.programmable counter array........................................................................... 34 2. absolute maximum ratings .................................................................................. 35 3. global dc electrical characteristics .................................................................... 36 4. pinout and package definitions............................................................................ 41 5. 12-bit adc (adc0).................................................................................................. 51 5.1. analog multiplexer ............................................................................................ 51 5.2. temperature sensor ......................................................................................... 52 5.3. adc0 operation................................................................................................ 52 5.3.1. starting a conversion............................................................................... 53 5.3.2. tracking modes........................................................................................ 53 5.3.3. timing....................................................................................................... 54 5.3.4. burst mode ............................................................................................... 56 5.3.5. output conversion code.......................................................................... 57 5.3.6. settling time requirements ..................................................................... 58 5.4. programmable window detector ...................................................................... 63 5.4.1. window detector in single-ended mode ................................................. 66 6. 12-bit current mode dacs (ida0 and ida1) ........................................................ 69 6.1. idac output scheduling................................................................................... 69 6.1.1. update output on-demand ..................................................................... 69 6.1.2. update output based on timer overflow ................................................ 70 6.1.3. update output based on cnvstr edge................................................. 70 6.2. idac output mapping....................................................................................... 70 6.3. idac external pin connections ........................................................................ 73 7. voltage reference .................................................................................................. 77 8. voltage regulator (reg0)...................................................................................... 81 9. comparators ......................................................................................................... 83
C8051F410/1/2/3 4 rev. 0.8 10. cip-51 microcontroller ........................................................................................... 93 10.1.instruction set................................................................................................... 94 10.1.1.instruction and cpu timing ..................................................................... 94 10.1.2.movx instruction and program memory ................................................. 95 10.2.register descriptions ....................................................................................... 98 10.3.power management modes............................................................................ 101 10.3.1.idle mode ............................................................................................... 102 10.3.2.stop mode.............................................................................................. 102 10.3.3.suspend mode ....................................................................................... 102 11. memory organization and sfrs ......................................................................... 103 11.1.program memory............................................................................................ 103 11.2.data memory .................................................................................................. 104 11.3.general purpose registers ............................................................................ 104 11.4.bit addressable locations .............................................................................. 104 11.5.stack............................................................................................................... 104 11.6.special function registers... .......................................................................... 105 12. interrupt handler .................................................................................................. 110 12.1.mcu interrupt sources and vectors............................................................... 110 12.2.interrupt priorities ........................................................................................... 110 12.3.interrupt latency............................................................................................. 110 12.4.interrupt register descriptions ....................................................................... 112 12.5.external interrupts .......................................................................................... 117 13. prefetch engine .................................................................................................... 119 14. cyclic redundancy check unit (crc0) ............................................................. 121 14.1.crc algorithm................................................................................................ 121 14.2.preparing for a crc calculation .................................................................... 123 14.3.performing a crc calculation ....................................................................... 123 14.4.accessing the crc0 result ........................................................................... 123 14.5.crc0 bit reverse feature............................................................................. 123 15. reset sources....................................................................................................... 127 15.1.power-on reset ............................................................................................. 128 15.2.power-fail reset / vdd monitor .................................................................... 129 15.3.external reset ................................................................................................ 130 15.4.missing clock detector reset ........................................................................ 130 15.5.comparator0 reset ........................................................................................ 130 15.6.pca watchdog timer reset .......................................................................... 131 15.7.flash error reset ........................................................................................... 131 15.8.smartclock (real time clock) reset........................................................... 132 15.9.software reset ............................................................................................... 132 16. flash memory ....................................................................................................... 135 16.1.programming the flash memory ................................................................... 135 16.1.1.flash lock and key functions ............................................................... 135 16.1.2.flash erase procedure .......................................................................... 135 16.1.3.flash write procedure ........................................................................... 136 16.2.non-volatile data storage .............................................................................. 137
rev. 0.8 5 C8051F410/1/2/3 16.3.security options ............................................................................................. 137 16.4.flash write and erase guidelines .................................................................. 139 16.4.1.vdd maintenance and the vdd monitor ............................................... 139 16.4.2.16.4.2 pswe maintenance .................................................................... 140 16.4.3.system clock ......................................................................................... 140 16.5.flash read timing ......................................................................................... 142 17. external ram ........................................................................................................ 145 18. port input/output.................................................................................................. 147 18.1.priority crossbar decoder .............................................................................. 149 18.2.port i/o initialization ....................................................................................... 151 18.3.general purpose port i/o ............................................................................... 154 19. oscillators ............................................................................................................. 165 19.1.programmable internal oscillator ................................................................... 165 19.1.1.internal oscillator suspend mode .......................................................... 166 19.2.external oscillator drive circuit ...................................................................... 168 19.2.1.clocking timers directly through the external oscillator...................... 168 19.2.2.external crystal example....................................................................... 168 19.2.3.external rc example............................................................................. 170 19.2.4.external capacitor example................................................................... 170 19.3.clock multiplier ............................................................................................... 172 19.4.system clock selection.................................................................................. 174 20. smartclock (real time clock)........................................................................... 177 20.1.smartclock interface .................................................................................... 178 20.1.1.smartclock lock and key functions ................................................... 178 20.1.2.using rtc0adr and rtc0dat to access smartclock internal registers ................................................. 178 20.1.3.smartclock interface autoread feature............................................... 178 20.1.4.rtc0adr autoincrement feature......................................................... 179 20.2.smartclock clocking sources ...................................................................... 182 20.2.1.using the smartclock oscillator in crystal mode ................................ 182 20.2.2.using the smartclock oscillator in self-oscillate mode ...................... 182 20.2.3.automatic gain control (crystal mode only) ......................................... 183 20.2.4.smartclock bias doubling ................................................................... 183 20.2.5.smartclock missing clock detector..................................................... 183 20.3.smartclock timer and alarm function......................................................... 185 20.3.1.setting and reading the smartclock timer value............................... 185 20.3.2.setting a smart clock alarm ................................................................. 186 20.4.backup regulator and ram ........................................................................... 187 21. smbus ................................................................................................................... 191 21.1.supporting documents ................................................................................... 192 21.2.smbus configuration...................................................................................... 192 21.3.smbus operation ........................................................................................... 192 21.3.1.arbitration............................................................................................... 193 21.3.2.clock low extension.............................................................................. 193 21.3.3.scl low timeout................................................................................... 194
C8051F410/1/2/3 6 rev. 0.8 21.3.4.scl high (smbus free) timeout .......................................................... 194 21.4.using the smbus............................................................................................ 194 21.4.1.smbus configuration register............................................................... 195 21.4.2.smb0cn control register ..................................................................... 198 21.4.3.data register ......................................................................................... 201 21.5.smbus transfer modes.................................................................................. 201 21.5.1.master transmitter mode ....................................................................... 201 21.5.2.master receiver mode ........................................................................... 202 21.5.3.slave receiver mode ............................................................................. 203 21.5.4.slave transmitter mode ......................................................................... 204 21.6.smbus status decoding................................................................................. 204 22. uart0.................................................................................................................... 207 22.1.enhanced baud rate generation................................................................... 208 22.2.operational modes ......................................................................................... 209 22.2.1.8-bit uart ............................................................................................. 209 22.2.2.9-bit uart ............................................................................................. 210 22.3.multiprocessor communications .................................................................... 210 23. enhanced serial peripheral interface (spi0)...................................................... 217 23.1.signal descriptions......................................................................................... 218 23.1.1.master out, slave in (mosi).................................................................. 218 23.1.2.master in, slave out (miso).................................................................. 218 23.1.3.serial clock (sck) ................................................................................. 218 23.1.4.slave select (nss) ................................................................................ 218 23.2.spi0 master mode operation ......................................................................... 219 23.3.spi0 slave mode operation ........................................................................... 220 23.4.spi0 interrupt sources ................................................................................... 221 23.5.serial clock timing......................................................................................... 221 23.6.spi special function registers ...................................................................... 222 24. timers.................................................................................................................... 23 1 24.1.timer 0 and timer 1 ....................................................................................... 231 24.1.1.mode 0: 13-bit counter/timer ................................................................ 231 24.1.2.mode 1: 16-bit counter/timer ................................................................ 233 24.1.3.mode 2: 8-bit counter/timer with auto-reload...................................... 233 24.1.4.mode 3: two 8-bit counter/timers (timer 0 only)................................. 234 24.2.timer 2 .......................................................................................................... 239 24.2.1.16-bit timer with auto-reload................................................................ 239 24.2.2.8-bit timers with auto-reload................................................................ 240 24.2.3.external/smartclock capture mode..................................................... 241 24.3.timer 3 .......................................................................................................... 244 24.3.1.16-bit timer with auto-reload................................................................ 244 24.3.2.8-bit timers with auto-reload................................................................ 245 24.3.3.external/smartclock capture mode..................................................... 246 25. programmable counter array (pca0) ................................................................ 249 25.1.pca counter/timer ........................................................................................ 250 25.2.capture/compare modules ............................................................................ 251
rev. 0.8 7 C8051F410/1/2/3 25.2.1.edge-triggered capture mode................................................................ 252 25.2.2.software timer (compare) m ode........................................................... 253 25.2.3.high speed output mode....................................................................... 254 25.2.4.frequency output mode ........................................................................ 255 25.2.5.8-bit pulse width modulator mode......................................................... 256 25.2.6.16-bit pulse width modulator mode....................................................... 257 25.3.watchdog timer mode ................................................................................... 257 25.3.1.watchdog timer operation .................................................................... 258 25.3.2.watchdog timer usage ......................................................................... 259 25.4.register descriptions for pca........................................................................ 261 26. c2 interface ........................................................................................................... 265 26.1.c2 interface registers.................................................................................... 265 26.2.c2 pin sharing ............................................................................................... 267 document change list............................................................................................. 268 contact information.................................................................................................. 270
C8051F410/1/2/3 8 rev. 0.8 n otes :
rev. 0.8 9 C8051F410/1/2/3 list of figures 1. system overview figure 1.1. C8051F410 block diagram .................................................................... 21 figure 1.2. c8051f411 block diagram .................................................................... 22 figure 1.3. c8051f412 block diagram .................................................................... 23 figure 1.4. c8051f413 block diagram .................................................................... 24 figure 1.5. development/in-system debug diagram............................................... 26 figure 1.6. memory map .......................................................................................... 27 figure 1.7. 12-bit adc block diagram..................................................................... 29 figure 1.8. idac block diagram .............................................................................. 30 figure 1.9. comparators block diagram .................................................................. 31 figure 1.10. smartclock block diagram ................................................................ 32 figure 1.11. port i/o functional bl ock diagram ....................................................... 33 figure 1.12. pca block diagram.............................................................................. 34 2. absolute maximum ratings 3. global dc electrical characteristics 4. pinout and package definitions figure 4.1. lqfp-32 pinout diagram (top view) .................................................... 44 figure 4.2. qfn-28 pin out diagram (top view) ...................................................... 45 figure 4.3. lqfp-32 package diagram ................................................................... 46 figure 4.4. qfn-28 package drawing ..................................................................... 47 figure 4.5. typical qfn-28 landing diagram.......................................................... 48 figure 4.6. typical qfn-28 solder paste mask....................................................... 49 5. 12-bit adc (adc0) figure 5.1. adc0 functional block diagram............................................................ 51 figure 5.2. typical temperature sensor transfer function..................................... 52 figure 5.3. adc0 tracking modes ........................................................................... 54 figure 5.4. 12-bit adc tracking mode example ..................................................... 55 figure 5.5. 12-bit adc burst mode example with repeat count set to 4............... 56 figure 5.6. adc0 equivalent input circuits.............................................................. 58 figure 5.7. adc window compare example: right-justified single-ended data ... 66 figure 5.8. adc window compare example: left-justified single-ended data ..... 66 6. 12-bit current mode dacs (ida0 and ida1) figure 6.1. idac functional block diagram............................................................. 69 figure 6.2. idac data word mapping...................................................................... 70 figure 6.3. idac pin connections ........................................................................... 74 7. voltage reference figure 7.1. voltage reference functional block diagram ....................................... 77 8. voltage regulator (reg0) figure 8.1. external capacitors for voltage regulator input/output ........................ 81 figure 8.2. external capacitors for voltage regulator input/output ........................ 81 9. comparators figure 9.1. comparator0 functional block diagram ................................................ 83 figure 9.2. comparator1 functional block diagram ................................................ 84
C8051F410/1/2/3 10 rev. 0.8 figure 9.3. comparator hysteresis plot ................................................................... 85 10. cip-51 microcontroller figure 10.1. cip-51 block diagram.......................................................................... 93 11. memory organization and sfrs figure 11.1. memory map ...................................................................................... 103 12. interrupt handler 13. prefetch engine 14. cyclic redundancy check unit (crc0) figure 14.1. crc0 block diagram ......................................................................... 121 figure 14.2. bit reverse register .......................................................................... 123 15. reset sources figure 15.1. reset sources.................................................................................... 127 figure 15.2. power-on and vdd monitor reset timing ........................................ 128 16. flash memory figure 16.1. flash program memory map.............................................................. 137 17. external ram 18. port input/output figure 18.1. port i/o functional bl ock diagram ..................................................... 147 figure 18.2. port i/o cell block diagram ............................................................... 148 figure 18.3. crossbar prio rity decoder with no pins skipped ............................... 149 figure 18.4. crossbar prio rity decoder with crystal pins skipped ........................ 150 figure 18.5. port 0 input overdrive current range................................................ 152 19. oscillators figure 19.1. oscillator diagram.............................................................................. 165 figure 19.2. 32.768 khz external cryst al example................................................ 169 figure 19.3. example clock multiplier output ........................................................ 172 20. smartclock (real time clock) figure 20.1. smartclock block diagram .............................................................. 177 21. smbus figure 21.1. smbus block diagram ....................................................................... 191 figure 21.2. typical smbus configur ation ............................................................. 192 figure 21.3. smbus transaction ............................................................................ 193 figure 21.4. typical smbus scl generation......................................................... 196 figure 21.5. typical master transmitter sequence................................................ 202 figure 21.6. typical master receiver sequence.................................................... 202 figure 21.7. typical slave receiver sequence...................................................... 203 figure 21.8. typical slave transmitte r sequence.................................................. 204 22. uart0 figure 22.1. uart0 block diagram ....................................................................... 207 figure 22.2. uart0 baud rate logic .................................................................... 208 figure 22.3. uart interconnect diagram .............................................................. 209 figure 22.4. 8-bit uart timing diagram............................................................... 209 figure 22.5. 9-bit uart timing diagram............................................................... 210 figure 22.6. uart multi-processor mode interconnect diagram .......................... 211
rev. 0.8 11 C8051F410/1/2/3 23. enhanced serial peripheral interface (spi0) figure 23.1. spi block diagram ............................................................................. 217 figure 23.2. multiple-master mode connection diagram ....................................... 220 figure 23.3. 3-wire single master an d slave mode connection diagram ............. 220 figure 23.4. 4-wire single master an d slave mode connection diagram ............. 220 figure 23.5. data/clock timing relationship ......................................................... 222 figure 23.6. spi master timing (ckpha = 0)........................................................ 227 figure 23.7. spi master timing (ckpha = 1)........................................................ 227 figure 23.8. spi slave timing (ckpha = 0).......................................................... 228 figure 23.9. spi slave timing (ckpha = 1).......................................................... 228 24. timers figure 24.1. t0 mode 0 block diagram.................................................................. 232 figure 24.2. t0 mode 2 block diagram.................................................................. 233 figure 24.3. t0 mode 3 block diagram.................................................................. 234 figure 24.4. timer 2 16-bit mode block diagram .................................................. 239 figure 24.5. timer 2 8-bit mode block diagram .................................................... 240 figure 24.6. timer 2 capture mode block diagram ............................................... 241 figure 24.7. timer 3 16-bit mode block diagram .................................................. 244 figure 24.8. timer 3 8-bit mode block diagram .................................................... 245 figure 24.9. timer 3 capture mode block diagram ............................................... 246 25. programmable c ounter array (pca0) figure 25.1. pca block diagram............................................................................ 249 figure 25.2. pca counter/timer block diagram.................................................... 250 figure 25.3. pca interrupt block diagram ............................................................. 251 figure 25.4. pca capture mode diagram.............................................................. 252 figure 25.5. pca software timer mode diagram .................................................. 253 figure 25.6. pca high-speed output mode diagram............................................ 254 figure 25.7. pca frequency output mode ............................................................ 255 figure 25.8. pca 8-bit pwm mode diagram ......................................................... 256 figure 25.9. pca 16-bit pwm mode...................................................................... 257 figure 25.10. pca module 5 with watchdog timer enabled ................................. 258 26. c2 interface figure 26.1. typical c2 pin sharing....................................................................... 267
C8051F410/1/2/3 12 rev. 0.8 n otes :
rev. 0.8 13 C8051F410/1/2/3 list of tables 1. system overview table 1.1. product selection guide ......................................................................... 20 table 1.2. operating modes summary .................................................................... 28 2. absolute maximum ratings table 2.1. absolute maximum ratings .................................................................... 35 3. global dc electrical characteristics table 3.1. global dc electrical charac teristics ....................................................... 36 table 3.2. index to electr ical characteristics tables ............................................... 39 4. pinout and package definitions table 4.1. pin definitions for the c8051f41x .......................................................... 41 table 4.2. lqfp-32 package dimensions .............................................................. 46 table 4.3. qfn-28 package dimensions ................................................................ 47 5. 12-bit adc (adc0) table 5.1. adc0 examples of right- and left-justified samples ........................... 57 table 5.2. adc0 repeat count examples at various input voltages ..................... 57 table 5.3. adc0 electrical characteristics (v dd = 2.5 v, v ref = 2.2 v) ................ 67 table 5.4. adc0 electrical characteristics (v dd = 2.1 v, v ref = 1.5 v) ................ 68 6. 12-bit current mode dacs (ida0 and ida1) table 6.1. idac electric al characteristics ............................................................... 75 7. voltage reference table 7.1. voltage reference electrical characteristics ......................................... 79 8. voltage regulator (reg0) table 8.1. voltage regulator electrical specifications ............................................ 82 9. comparators table 9.1. comparator electrical char acteristics .................................................... 92 10. cip-51 microcontroller table 10.1. cip-51 instruction set summary .......................................................... 95 11. memory organization and sfrs table 11.1. special function register (sfr) memory map .................................. 105 table 11.2. special function registers ................................................................. 106 12. interrupt handler table 12.1. interrupt summary .............................................................................. 111 13. prefetch engine 14. cyclic redundancy check unit (crc0) table 14.1. example 16-bit crc outputs ............................................................. 122 15. reset sources table 15.1. reset electrical characte ristics .......................................................... 134 16. flash memory table 16.1. flash security summary .................................................................... 138 table 16.2. flash electrical characte ristics .......................................................... 143 17. external ram
C8051F410/1/2/3 14 rev. 0.8 18. port input/output table 18.1. port i/o dc electrical characteristics ................................................. 163 19. oscillators table 19.1. oscillator electrical characteristics .................................................... 175 20. smartclock (real time clock) table 20.1. smartclock internal registers .......................................................... 179 21. smbus table 21.1. smbus clock source selection .......................................................... 195 table 21.2. minimum sda setup and hold times ................................................ 196 table 21.3. sources for hardware changes to smb0cn ..................................... 200 table 21.4. smbus status decoding ..................................................................... 205 22. uart0 table 22.1. timer settings for standard baud rates using the internal oscillator ............................................................... 214 table 22.2. timer settings for standard baud rates using an external 25.0 mhz oscillator ............................................... 214 table 22.3. timer settings for standard baud rates using an external 22.1184 mhz oscillator ......................................... 215 table 22.4. timer settings for standard baud rates using an external 18.432 mhz oscillator ........................................... 215 table 22.5. timer settings for standard baud rates using an external 11.0592 mhz oscillator ......................................... 216 table 22.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator ........................................... 216 23. enhanced serial peripheral interface (spi0) table 23.1. spi slave timing parameters ............................................................ 229 24. timers 25. programmable c ounter array (pca0) table 25.1. pca timebase input options ............................................................. 250 table 25.2. pca0cpm register settings for pca capture/compare modules .... 251 table 25.3. watchdog timer timeout intervals...................................................... 260 26. c2 interface
rev. 0.8 15 C8051F410/1/2/3 list of registers sfr definition 5.1. adc0mx: adc0 channel select . . . . . . . . . . . . . . . . . . . . . . . . . . 59 sfr definition 5.2. adc0cf: adc0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sfr definition 5.3. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sfr definition 5.4. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sfr definition 5.5. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sfr definition 5.6. adc0tk: adc0 tracking mode select . . . . . . . . . . . . . . . . . . . . 63 sfr definition 5.7. adc0gth: adc0 greater-than data high byte . . . . . . . . . . . . . 64 sfr definition 5.8. adc0gtl: adc0 greater-than data low byte . . . . . . . . . . . . . . 64 sfr definition 5.9. adc0lth: adc0 less-than data high byte . . . . . . . . . . . . . . . . 65 sfr definition 5.10. adc0ltl: adc0 less-than da ta low byte . . . . . . . . . . . . . . . . 65 sfr definition 6.1. ida0cn: ida0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 sfr definition 6.2. ida0h: ida0 data high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 sfr definition 6.3. ida0l: ida0 data low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 sfr definition 6.4. ida1cn: ida1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 sfr definition 6.5. ida1h: ida0 da ta high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 sfr definition 6.6. ida1l: ida1 data low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 sfr definition 7.1. ref0cn: reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 sfr definition 8.1. reg0cn: regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 9.1. cpt0cn: comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sfr definition 9.2. cpt0mx: comparator0 mux selection . . . . . . . . . . . . . . . . . . . . 87 sfr definition 9.3. cpt0md: comparator0 mode se lection . . . . . . . . . . . . . . . . . . . . 88 sfr definition 9.4. cpt1mx: comparator1 mux selection . . . . . . . . . . . . . . . . . . . . 89 sfr definition 9.5. cpt1md: comparator1 mode se lection . . . . . . . . . . . . . . . . . . . . 90 sfr definition 9.6. cpt1cn: comparator1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 sfr definition 10.1. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 sfr definition 10.2. dpl: data pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 sfr definition 10.3. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 sfr definition 10.4. psw: program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 sfr definition 10.5. acc: accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 sfr definition 10.6. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 sfr definition 10.7. pcon: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 sfr definition 12.1. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 12.2. ip: interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 12.3. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . 114 sfr definition 12.4. eip1: extended interrupt priori ty 1 . . . . . . . . . . . . . . . . . . . . . . 115 sfr definition 12.5. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . . 116 sfr definition 12.6. eip2: extended interrupt priori ty 2 . . . . . . . . . . . . . . . . . . . . . . 116 sfr definition 12.7. it01cf: int0/int1 configuratio n . . . . . . . . . . . . . . . . . . . . . . . 118 sfr definition 13.1. pfe0cn: prefetch engine control . . . . . . . . . . . . . . . . . . . . . . 119 sfr definition 14.1. crc0cn: crc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 sfr definition 14.2. crc0in: crc0 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 sfr definition 14.3. crc0dat: crc0 data output . . . . . . . . . . . . . . . . . . . . . . . . . 125 sfr definition 14.4. crc0flip: crc0 bit flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
C8051F410/1/2/3 16 rev. 0.8 sfr definition 15.1. vdm0cn: vdd monitor control . . . . . . . . . . . . . . . . . . . . . . . . 130 sfr definition 15.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sfr definition 16.1. psctl: program store r/w control . . . . . . . . . . . . . . . . . . . . . 141 sfr definition 16.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 sfr definition 16.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 sfr definition 16.4. oneshot: flash oneshot period . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 17.1. emi0cn: exte rnal memory interface control . . . . . . . . . . . . . . 145 sfr definition 18.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 153 sfr definition 18.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 154 sfr definition 18.3. p0: port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 sfr definition 18.4. p0mdin: port0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 sfr definition 18.5. p0mdout: port0 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 156 sfr definition 18.6. p0skip: port0 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 sfr definition 18.7. p0mat: port0 match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 18.8. p0mask: port0 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 18.9. p0oden: port0 overdrive mode . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 18.10. p1: port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 sfr definition 18.11. p1mdin: port1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 sfr definition 18.12. p1mdout: po rt1 output mode . . . . . . . . . . . . . . . . . . . . . . . . 159 sfr definition 18.13. p1skip: port1 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 sfr definition 18.14. p1mat: port1 match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 sfr definition 18.15. p1mask: port1 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 sfr definition 18.16. p2: port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 sfr definition 18.17. p2mdin: port2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 sfr definition 18.18. p2mdout: po rt2 output mode . . . . . . . . . . . . . . . . . . . . . . . . 162 sfr definition 18.19. p2skip: port2 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 sfr definition 19.1. oscicn: internal oscillator control . . . . . . . . . . . . . . . . . . . . . 167 sfr definition 19.2. oscicl: internal oscillator calibration . . . . . . . . . . . . . . . . . . . 167 sfr definition 19.3. oscxcn: external oscillator control . . . . . . . . . . . . . . . . . . . . 171 sfr definition 19.4. clkmul: clock multiplier control . . . . . . . . . . . . . . . . . . . . . . . 173 sfr definition 19.5. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 sfr definition 20.1. rtc0key: smartclock lock and key . . . . . . . . . . . . . . . . . . . 180 sfr definition 20.2. rtc0adr: smartclock address . . . . . . . . . . . . . . . . . . . . . . 181 sfr definition 20.3. rtc0dat: smartclock data . . . . . . . . . . . . . . . . . . . . . . . . . 182 internal register definition 20.4. rtc0cn: smar tclock control . . . . . . . . . . . . . . . 184 internal register definition 20.5. rtc0xcn: smartclock oscillator control . . . . . . 185 internal register definition 20.6. capturen: smartclock timer capture . . . . . . . 186 internal register definition 20.7. alarmn: smar tclock alarm . . . . . . . . . . . . . . . . 187 internal register definition 20.8. rama ddr: smartclock backup ram address . . 187 internal register definition 20.9. ramdat a: smartclock backup ram data . . . . . 188 sfr definition 21.1. smb0cf: smbus clock/configur ation . . . . . . . . . . . . . . . . . . . 197 sfr definition 21.2. smb0cn: smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 sfr definition 21.3. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 sfr definition 22.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 212 sfr definition 22.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 213
rev. 0.8 17 C8051F410/1/2/3 sfr definition 23.1. spi0cfg: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 223 sfr definition 23.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 sfr definition 23.3. spi0ckr: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 sfr definition 23.4. spi0dat: spi0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 sfr definition 24.1. tcon: timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 sfr definition 24.2. tmod: timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 sfr definition 24.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 sfr definition 24.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 sfr definition 24.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 sfr definition 24.6. th0: timer 0 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 sfr definition 24.7. th1: timer 1 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 sfr definition 24.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 24.9. tmr2rll: timer 2 reload register low byte . . . . . . . . . . . . . 243 sfr definition 24.10. tmr2rlh: timer 2 reload register high byte . . . . . . . . . . . 243 sfr definition 24.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 sfr definition 24.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 sfr definition 24.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 sfr definition 24.14. tmr3rll: timer 3 reload register low byte . . . . . . . . . . . . 248 sfr definition 24.15. tmr3rlh: timer 3 reload register high byte . . . . . . . . . . . 248 sfr definition 24.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 sfr definition 24.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 sfr definition 25.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 sfr definition 25.2. pca0md: pca mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 sfr definition 25.3. pca0cpmn: pca capture/co mpare mode . . . . . . . . . . . . . . . 263 sfr definition 25.4. pca0l: pca counter/timer lo w byte . . . . . . . . . . . . . . . . . . . 264 sfr definition 25.5. pca0h: pca counter/timer high byte . . . . . . . . . . . . . . . . . . . 264 sfr definition 25.6. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 264 sfr definition 25.7. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 264 c2 register definition 26.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 c2 register definition 26.2. deviceid: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 265 c2 register definition 26.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 266 c2 register definition 26.4. fpctl: c2 flash programming control . . . . . . . . . . . . 266 c2 register definition 26.5. fpdat: c2 flash programming data . . . . . . . . . . . . . . 266
C8051F410/1/2/3 18 rev. 0.8 n otes :
rev. 0.8 19 C8051F410/1/2/3 1. system overview c8051f41x devices are fully integrated, low power, mixed-signal system-on-a-chip mcus. highlighted fea - tures are listed below. refer to table 1.1 for specific product feature selection. high-speed pipelined 8051-compatible microcontroller core (up to 50 mips) in-system, full-speed, non-intrusive debug interface (on-chip) true 12-bit 200 ksps adc with analog multiplexer and 24 analog inputs two 12-bit current output dacs precision programmable 24.5 mhz internal oscillator up to 32 kb bytes of on-chip flash memory 2304 bytes of on-chip ram smbus/i2c, enhanced uart, and spi serial interfaces implemented in hardware four general-purpose 16-bit timers programmable counter/timer array (pca) with six capture/compare modules and watchdog timer function hardware smartclock (real time clock) operates down to 1 v with 64 bytes of backup ram and a backup voltage regulator hardware crc engine on-chip power-on reset, v dd monitor, and temperature sensor on-chip voltage comparators up to 24 port i/o with on-chip power-on reset, v dd monitor, watchdog timer, and clock oscillator, the c8051f41x devices are truly standalone system-on-a-chip solutions. the flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. the on-chip silicon laboratories 2-wire (c2) development interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in-system programming and debugging without occupying package pins. each device is specified for 2.0-to-2.75 v operation (supply voltage can be up to 5.25 v using on-chip reg - ulator) over the industrial temperature range (?45 to +85 c). the c8051f41x are available in 28-pin qfn (also referred to as mlp or mlf) or 32-pin lqfp packages.
C8051F410/1/2/3 20 rev. 0.8 table 1.1. product selection guide ordering part number mips (peak) flash memory ram calibrated internal 24.5 mhz oscillator clock multiplier smbus/i2c spi uart timers (16-bit) programmable counter array port i/os 12-bit adc 1 lsb inl smartclock (real time clock) two 12-bit current output dacs internal voltage reference temperature sensor analog comparators lead-free (rohs compliant) package C8051F410-gq 50 32 kb 2368 3 3 3 3 3 4 3 24 3 3 3 3 3 3 3 lqfp-32 c8051f411-gm 50 32 kb 2368 3 3 3 3 3 4 3 20 3 3 3 3 3 3 3 qfn-28 c8051f412-gq 50 16 kb 2368 3 3 3 3 3 4 3 24 3 3 3 3 3 3 3 lqfp-32 c8051f413-gm 50 16 kb 2368 3 3 3 3 3 4 3 20 3 3 3 3 3 3 3 qfn-28
rev. 0.8 21 C8051F410/1/2/3 figure 1.1. C8051F410 block diagram uart 32 kb flash 256 b sram por sfr bus 8 0 5 1 c o r e x16 reset /rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 2 kb xram xtal1 xtal2 p0.0/idac0 p0.1/idac1 p0.2 p0.3 p0.4/tx p0.5/rx p0.6/cnvst p0.7 spi vdd c r o s s b a r p 1 d r v p1.0/xtal1 p1.1/xtal2 p1.2/vref p1.3 p1.4 p1.5 p1.6 p1.7 port 0 latch smbus timer 0,1,2,3 port 1 latch 24.5 mhz 2% oscillator p 2 d r v p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7/c2d 12-bit 200 ksps adc a m u x ain0-ain23 vdd cp1 + - temp cp0 + - c2d port 2 latch pca x6 / wdt 32 khz oscillator gnd vref smartclock state machine vrtc-backup 12-bit idac0 idac0 smartclock alarm smartclock block (to smarrtclock block) (to rest of chip) battery switch-over circuit (vdd >= vrtc-backup) clock mult. xtal3 xtal4 vreg vregin vio 12-bit idac1 idac1 64b ram crc engine
C8051F410/1/2/3 22 rev. 0.8 figure 1.2. c8051f411 block diagram uart 32 kb flash 256 b sram por sfr bus 8 0 5 1 c o r e x16 reset /rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 2 kb xram xtal1 xtal2 p0.0/idac0 p0.1/idac1 p0.2 p0.3 p0.4/tx p0.5/rx p0.6/cnvst p0.7 spi vdd c r o s s b a r p 1 d r v p1.0/xtal1 p1.1/xtal2 p1.2/vref p1.3 p1.4 p1.5 p1.6 p1.7 port 0 latch smbus timer 0,1,2,3 port 1 latch 24.5 mhz 2% oscillator p 2 d r v p2.0 p2.1 p2.2 p2.7/c2d 12-bit 200 ksps adc a m u x ain0-ain20 vdd cp1 + - temp cp0 + - c2d port 2 latch pca x6 / wdt 32 khz oscillator gnd vref smartclock state machine vrtc-backup 12-bit idac0 idac0 smartclock alarm smartclock block (to smartclock block) (to rest of chip) battery switch-over circuit (vdd >= vrtc-backup) clock mult. xtal3 xtal4 vreg vregin vio 12-bit idac1 idac1 64b ram crc engine
rev. 0.8 23 C8051F410/1/2/3 figure 1.3. c8051f412 block diagram uart 16 kb flash 256 b sram por sfr bus 8 0 5 1 c o r e x16 reset /rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 2 kb xram xtal1 xtal2 p0.0/idac0 p0.1/idac1 p0.2 p0.3 p0.4/tx p0.5/rx p0.6/cnvst p0.7 spi vdd c r o s s b a r p 1 d r v p1.0/xtal1 p1.1/xtal2 p1.2/vref p1.3 p1.4 p1.5 p1.6 p1.7 port 0 latch smbus timer 0,1,2,3 port 1 latch 24.5 mhz 2% oscillator p 2 d r v p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7/c2d 12-bit 200 ksps adc a m u x ain0-ain23 vdd cp1 + - temp cp0 + - c2d port 2 latch pca x6 / wdt 32 khz oscillator gnd vref smartclock state machine vrtc-backup 12-bit idac0 idac0 smartclock alarm smartclock block (to smartclocl block) (to rest of chip) battery switch-over circuit (vdd >= vrtc-backup) clock mult. xtal3 xtal4 vreg vregin vio 12-bit idac1 idac1 64b ram crc engine
C8051F410/1/2/3 24 rev. 0.8 figure 1.4. c8051f413 block diagram uart 16 kb flash 256 b sram por sfr bus 8 0 5 1 c o r e x16 reset /rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 2 kb xram xtal1 xtal2 p0.0/idac0 p0.1/idac1 p0.2 p0.3 p0.4/tx p0.5/rx p0.6/cnvst p0.7 spi vdd c r o s s b a r p 1 d r v p1.0/xtal1 p1.1/xtal2 p1.2/vref p1.3 p1.4 p1.5 p1.6 p1.7 port 0 latch smbus timer 0,1,2,3 port 1 latch 24.5 mhz 2% oscillator p 2 d r v p2.0 p2.1 p2.2 p2.7/c2d 12-bit 200 ksps adc a m u x ain0-ain20 vdd cp1 + - temp cp0 + - c2d port 2 latch pca x6 / wdt 32 khz oscillator gnd vref smartclock state machine vrtc-backup 12-bit idac0 idac0 smartclock alarm smartclock block (to smartclock block) (to rest of chip) battery switch-over circuit (vdd >= vrtc-backup) clock mult. xtal3 xtal4 vreg vregin vio 12-bit idac1 idac1 64b ram crc engine
rev. 0.8 25 C8051F410/1/2/3 1.1. cip-51? microcontroller 1.1.1. fully 8051 compatible instruction set the c8051f41x devices use silicon laboratories? proprietary cip-51 microcontroller core. the cip-51 is fully compatible with the mcs-51? instruction set. standard 803x/805x assemblers and compilers can be used to develop software. the c8051f41x family has a superset of all the peripherals included with a stan - dard 8052. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan - dard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12-to-24 mhz. by contrast, the cip- 51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's system clock running at 50 mhz, it has a peak throughput of 50 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. 1.1.3. additional features the c8051f41x soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. an extended interrupt handler allows the numerous analog and digital peripherals to operate indepen - dently of the controller core and interrupt the controller only when necessary. by requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implemen - tation of multi-tasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor, a watchdog timer, a missing clock detector, a voltage level detection from comparator0, a smartclock alarm or missing smartclock clock detector reset, a forced software reset, an external reset pin, and an illegal flash access protection circuit. each reset source except for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently enabled in software after a power-on reset during mcu initialization. the internal oscillator is factory calibrated to 24.5 mhz 2%. an external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, rc, or cmos clock source to generate the system clock. a clock multiplier allows for operation at up to 50 mhz. the dedicated smartclock oscil - lator can be extremely useful in low power applications, allowing the system to maintain accurate time while the mcu is not powered, or its internal oscillator is suspended. the mcu can be reset or have its oscillator awakened using the smartclock alarm function. clocks to execute 1 2 2/4 3 3/5 4 5 4/6 6 8 number of instructions 26 50 5 10 7 5 2 1 2 1
C8051F410/1/2/3 26 rev. 0.8 1.2. on-chip debug circuitry the c8051f41x devices include on-chip silicon laboratories 2-wire (c2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. silicon laboratories? debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. no additional target ram, program memory, timers, or communications channels are required. all the digital and analog peripherals are functional and work correctly while debug - ging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the C8051F410dk development kit provides all the hardware and software necessary to develop applica - tion code and perform in-circuit debugging with the c8051f41x mcus. the kit includes software with a developer's studio and debugger, a usb debug adapter, a target application board with the associated mcu installed, and the required cables and wall-mount power supply. the development kit requires a com - puter with windows ? 98 se or later installed. as shown in figure 1.5 , the pc is connected to the usb debug adapter. a six-inch ribbon cable connects the usb debug adapter to the user's application board, picking up the two c2 pins and gnd. the silicon laboratories ide interface is a vastly superior developing and debugging configuration, com - pared to standard mcu emulators that use on-board "ice chips" and require the mcu in the application board to be socketed. silicon laboratories? debug paradigm increases ease of use and preserves the per - formance of the precision analog peripherals. figure 1.5. development/ in-system debug diagram target pcb usb debug adapter vdd gnd c2 (x2), gnd windows 98 se or later silicon laboratories integrated development environment c8051f41x
rev. 0.8 27 C8051F410/1/2/3 1.3. on-chip memory the cip-51 has a standard 8051 program and data address configuration. it includes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128-byte sfr address space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. program memory consists of 32 kb (?f410/1) or 16 kb (?f412/3) of flash. this memory may be repro - grammed in-system in 512 byte sectors and requires no special off-chip programming voltage. figure 1.6. memory map program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 2048 bytes (accessible using movx instruction) 0x0000 0x07ff same 2048 bytes as from 0x0000 to 0x07ff, wrapped on 2048-byte boundaries 0x0800 0xffff 32 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x7e00 0x7dff ?f410/1 16 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x4000 0x3fff ?f412/3
C8051F410/1/2/3 28 rev. 0.8 1.4. operating modes the c8051f41x devices have four operating modes: active (normal), idle, suspend, and stop. active mode occurs during normal operation when the oscillator and peripherals are active. idle mode halts the cpu while leaving the peripherals and internal clocks active. suspend mode halts sysclk until a waken - ing event occurs, which also halts all peripherals using sysclk. in stop mode, the cpu is halted, all inter - rupts and timers are inactive, and the internal oscillator is stopped. the various operating modes are described in table 1.2 below: see section ?10.3. power management modes? on page 101 for idle and stop mode details. see sec - tion ?19.1.1. internal oscillator suspend mode? on page 166 for more information on suspend mode. table 1.2. operating modes summary properties power consumption how entered? how exited? active sysclk active cpu active (accessing flash) peripherals active or inactive depending on user settings smartclock active or inactive full ? ? idle sysclk active cpu inactive (not accessing flash) peripherals active or inactive depending on user settings smartclock active or inactive less than full idle (pcon.0) any enabled interrupt or device reset suspend sysclk inactive cpu inactive (not accessing flash) peripherals enabled (but not operating) or disabled depend - ing on user settings smartclock active or inactive low suspend (oscicn.5) wakening event or exter - nal/mcd reset stop sysclk inactive cpu inactive (not accessing flash) digital peripherals inactive; analog peripherals enabled (but not operating) or disabled depending on user settings smartclock inactive very low stop (pcon.1) external or mcd reset
rev. 0.8 29 C8051F410/1/2/3 1.5. 12-bit analog to digital converter the c8051f41x devices include an on-chip 12-bit sar adc with a 27-channel single-ended input multi - plexer and a maximum throughput of 200 ksps. the adc system includes a configurable analog multi - plexer that selects the positive adc input, which is measured with respect to gnd. ports 0?2 are available as adc inputs; additionally, the on-chip temperature sensor output and the core supply voltage (v dd ) are available as adc inputs. user firmware may shut down the adc or use it in burst mode to save power. conversions can be started in four ways: a software command, an overflow of timer 2 or 3, or an external convert start signal. this flexibility allows the start of conversion to be triggered by software events, a peri - odic signal (timer overflows), or external hw signals. conversion completions are indicated by a status bit and an interrupt (if enabled) and occur after 1, 4, 8, or 16 samples have been accumulated by a hardware accumulator. the resulting data word is latched into the adc data sfrs upon completion of a conversion. when the system clock is slow, burst mode allows adc0 to automatically wake from a low power shut - down state, acquire and accumulate samples, then re-enter the low power shutdown state without cpu intervention. window compare registers for the adc data can be configured to interrupt the controller when adc data is either within or outside of a specified range. the adc can monitor a key voltage continuously in back - ground mode, but not interrupt the controller unless the converted data is within/outside the specified range. figure 1.7. 12-bit adc block diagram 1.6. two 12-bit current-mode dacs the c8051f41x devices include two 12-bit current-mode digital-to-analog converters (idacs). the maxi - mum current output of the idacs can be adjusted for four different current settings; 0.25 ma, 0.5 ma, 1 ma, and 2 ma. a flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free updates for waveform generation. the idac outputs can be merged onto a single port i/o pin for increased full-scale current output or increased resolution. idac updates can be performed on-demand, scheduled on a timer overflow, or synchronized with an external signal. figure 1.8 shows a block diagram of the idac circuitry. 12-bit sar adc timer 2 overflow configuration, control, and data registers timer 3 overflow cnvstr rising edge start conversion ad0busy (w) 16 window compare logic window compare interrupt adc data registers end of conversion interrupt 19-to-1 amux p1.0 p1.7 p2.0 p2.7 p2.3-2.6 available on C8051F410/2 analog multiplexer vdd temp sensor p0.0 p0.7 burst mode logic accumulator gnd
C8051F410/1/2/3 30 rev. 0.8 figure 1.8. idac block diagram 1.7. programmable comparators c8051f41x devices include two software-configurable voltage comparators with an input multiplexer. each comparator offers programmable response time and hysteresis and two outputs that are optionally avail - able at the port pins: a synchronous ?latched? output (cp0 and cp1), or an asynchronous ?raw? output (cp0a and cp1a). comparator interrupts may be generated on rising, falling, or both edges. when in idle or suspend mode, these interrupts may be used as a ?wake-up? source for the processor. comparator0 may also be configured as a reset source. a block diagram of the comparator is shown in figure 1.9 . ida0 12 latch 12 curre nt outpu t 1 2-bit digital input ida1 12 latch 12 curre nt outpu t 1 2-bit digital input data write timer 0 timer 1 timer 2 timer 3 cnvstr data write timer 0 timer 1 timer 2 timer 3 cnvstr
rev. 0.8 31 C8051F410/1/2/3 figure 1.9. comparators block diagram 1.8. cyclic redunda ncy check unit c8051f41x devices include a cyclic redundancy check unit (crc0) that can perform a crc using a 16-bit or 32-bit polynomial. crc0 accepts a stream of 8-bit data and outputs a 16-bit or 32-bit result. crc0 also has a hardware bit reverse feature for quick data manipulation. 1.9. voltage regulator c8051f41x devices include an on-chip low dropout voltage regulator (reg0). the input to reg0 at the v regin pin can be as high as 5.25 v. the output can be selected by software to 2.0 v or 2.5 v. when enabled, the output of reg0 powers the device and drives the v dd pin. the voltage regulator can be used to power external devices connected to v dd . 1.10. serial ports the c8051f41x family includes an smbus/i2c interface, a full-duplex uart with enhanced baud rate configuration, and an enhanced spi interface. each of the serial buses is fully implemented in hardware and makes extensive use of the cip-51's interrupts, thus requiring very little cpu intervention. vdd reset decision tree + - q q set clr d q q set clr d (synchronizer) gnd cp0 (synchronous output ) cp0a (asynchronous outpu t) interrupt logic multiplexer port i/o pins vdd + - q q set clr d q q set clr d (synchronizer) gnd cp1 (synchronous output ) cp1a (asynchronous outpu t) interrupt logic multiplexer port i/o pins
C8051F410/1/2/3 32 rev. 0.8 1.11. smartclock (real time clock) c8051f41x devices include a smartclock peripheral (real time clock). the smartclock has a dedi - cated 32 khz oscillator that can be configured for use with or without a crystal, a 47-bit smartclock timer with alarm, a backup supply regulator, and 64 bytes of backup sram. when the backup supply voltage (v rtc-backup ) is powered, the smartclock peripheral remains fully functional even if the core supply volt - age (v dd ) is lost. the smartclock allows a maximum of 137 year 47-bit independent time-keeping when used with a 32.768 khz watch crystal and backup supply voltage of at least 1 v. the switchover logic powers smart - clock from the backup supply when the voltage at v rtc-backup is greater than v dd . the smartclock alarm and missing clock detector can interrupt the cip-51, wake the internal oscillator from suspend mode, or generate a device reset if the smartclock timer reaches a pre-set value or the oscillator stops. figure 1.10. smartclock block diagram 64b backup ram smartclock oscillator smartclock cip-51 cpu xtal4 xtal3 switchover logic rtc0cn capturen alarmn rtc0xcn ramdata ramaddr rtc0key rtc0adr rtc0dat interface registers internal registers smartclock state machine interrupt backup regulator v dd v rtc-backup 47-bit smartclock timer
rev. 0.8 33 C8051F410/1/2/3 1.12. port input/output c8051f41x devices include up to 24 i/o pins. port pins are organized as three byte-wide ports. the port pins behave like typical 8051 ports with a few enhancements. each port pin can be configured as a digital or analog i/o pin. pins selected as digital i/o can be configured for push-pull or open-drain operation. the ?weak pullups? that are fixed on typical 8051 devices may be individually or globally disabled to save power. the digital crossbar allows mapping of internal digital system resources to port i/o pins. on-chip counter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the port pins using the crossbar control registers. this allows the user to select the exact mix of general- purpose port i/o, digital, and analog resources needed for the application. figure 1.11. port i/o functional block diagram xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 p0mask, p0match p1mask, p1match registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi 4 p1 i/o cells p1.0 p1.7 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 i/o cell p2 (p2.0-p2.7) 8 8 p2.0 p2.7 pnmdout, pnmdin registers p2.3?2.6 available on C8051F410/2
C8051F410/1/2/3 34 rev. 0.8 1.13. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. the pca consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. the counter/timer is driven by a programmable timebase that can select between seven sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, real-time clock source divided by 8, timer 0 over - flow, or an external clock signal on the external clock input (eci) pin. each capture/compare module may be configured to operate independently in one of six modes: edge- triggered capture, software timer, high-speed output, frequency output, 8-bit pwm, or 16-bit pwm. additionally, pca module 5 may be used as a watchdog timer (wdt), and is enabled in this mode follow - ing a system reset. the pca capture/compare module i/o and the external clock input may be routed to port i/o using the digital crossbar. figure 1.12. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 cex1 eci crossbar cex2 cex3 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 smartclock/8 capture/compare module 4 cex4 capture/compare module 5 cex5
rev. 0.8 35 C8051F410/1/2/3 2. absolute maximum ratings table 2.1. absolute maximum ratings* parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on v regin with respect to gnd ?0.3 ? 5.5 v voltage on v dd with respect to gnd ?0.3 ? 3.0 v voltage on v rtc-backup with respect to gnd ?0.3 ? 5.5 v voltage on xtal1 with respect to gnd ?0.3 ? v dd + 0.3 v voltage on xtal3 with respect to gnd ?0.3 ? 5.5 v voltage on any port i/o pin (except port 0 pins) or rst with respect to gnd ?0.3 ? v io + 0.3 v voltage on any port 0 pin with respect to gnd 0.3 ? 5.5 v maximum output current sunk by any port pin ? ? 100 ma maximum output current sourced by any port pin ? ? 100 ma maximum total current through v dd , v io , v rtc-backup , v regin , and gnd ??500ma *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
C8051F410/1/2/3 36 rev. 0.8 3. global dc electrical characteristics table 3.1. global dc electrical characteristics ?40 to +85 c, 50 mhz system clock unless otherwise specified. typical values are given at 25 c parameter conditions min typ max units supply input voltage (v regin ) output current = 1 ma (note 1) 2.15 ? 5.25 v core supply voltage (v dd ) 2.0 ? 2.75 v i/o supply voltage (v io ) 2.0 ? 5.25 v backup supply voltage (v rtc-backup ) (note 2) 1.0 ? 5.25 v backup supply current (i rtc-backup ) (v dd = 0 v, smartclock clock = 32 khz) v rtc-backup = 1.0 v: at ?40 oc at 25 oc at 85 oc v rtc-backup = 1.8 v: at ?40 oc at 25 oc at 85 oc v rtc-backup = 2.5 v: at ?40 oc at 25 oc at 85 oc ? ? ? ? ? ? ? ? ? 0.65 0.9 1.4 0.7 0.92 1.45 0.72 0.95 1.5 tbd tbd tbd tbd tbd tbd tbd tbd tbd a a a a a a a a a core supply ram data retention voltage ? tbd ? v sysclk (system clock) (notes 3 and 4) 0 ? 50 mhz specified operating temperature range ?40 ? +85 c notes: 1. for more information on v regin characteristics, see table 8.1 on page 82 . 2. the backup supply voltage (v rtc-backup ) is used to power the smartclock peripheral only. 3. sysclk is the internal device clock. for operational speeds in excess of 25 mhz, sysclk must be derived from the internal clock multiplier. 4. sysclk must be at least 32 khz to enable debugging. 5. based on device characterization data, not production tested. 6. active and inactive idd at voltages and frequencies other than those specified can be calculated using the idd supply sensitivity. for example, if the v dd is 2.2 v instead of 2.0 v at 25 mhz: i dd = tbd ma typical at 2.0 v and f = 25 mhz. from this, i dd = tbd ma + tbd x (2.2 v ? 2.0 v) = tbd ma at 2.2 v and f = 25 mhz. 7. i dd can be estimated for frequencies < tbd mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate i dd for > tbd mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 2.0 v; f = 20 mhz, i dd = tbd ma ? (25 mhz ? 20 mhz) x tbd ma/mhz = tbd ma. 8. idle idd can be estimated for frequencies < tbd mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate idle for > tbd mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 2.0 v; f = 5 mhz, idle i dd = tbd ma ? (25 mhz ? 5 mhz) x tbd ma/mhz = tbd ma.
rev. 0.8 37 C8051F410/1/2/3 digital supply current?cpu active (normal mode, fetching instructions from flash) core supply current (i dd ) (note 5) v dd = 2.0 v: f = 32 khz f = 1 mhz f = 25 mhz f = 50 mhz v dd = 2.5 v: f = 32 khz f = 1 mhz f = 25 mhz f = 50 mhz ? ? ? ? ? ? ? ? 13 0.30 5.5 9.5 17 0.43 8.3 13.5 tbd tbd ? tbd tbd tbd ? tbd a ma ma ma a ma ma ma supply sensitivity (i dd ) (notes 5 and 6) f = 25 mhz f = 1 mhz ? ? tbd tbd ? ? %/v %/v frequency sensitivity (i dd ) (notes 5 and 7) v dd = 2.0 v: f < 15 mhz, t = 25 oc f > 15 mhz, t = 25 oc v dd = 2.5 v: f < 15 mhz, t = 25 oc f > 15 mhz, t = 25 oc ? ? ? ? tbd tbd tbd tbd ? ? ? ? ma/mhz ma/mhz ma/mhz ma/mhz table 3.1. global dc electrical characteristics (continued) ?40 to +85 c, 50 mhz system clock unless otherwise specified. typical values are given at 25 c parameter conditions min typ max units notes: 1. for more information on v regin characteristics, see table 8.1 on page 82. 2. the backup supply voltage (v rtc-backup ) is used to power the smartclock peripheral only. 3. sysclk is the internal device clock. for operational speeds in excess of 25 mhz, sysclk must be derived from the internal clock multiplier. 4. sysclk must be at least 32 khz to enable debugging. 5. based on device characterization data, not production tested. 6. active and inactive idd at voltages and frequencies other than those specified can be calculated using the idd supply sensitivity. for example, if the v dd is 2.2 v instead of 2.0 v at 25 mhz: i dd = tbd ma typical at 2.0 v and f = 25 mhz. from this, i dd = tbd ma + tbd x (2.2 v ? 2.0 v) = tbd ma at 2.2 v and f = 25 mhz. 7. i dd can be estimated for frequencies < tbd mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate i dd for > tbd mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 2.0 v; f = 20 mhz, i dd = tbd ma ? (25 mhz ? 20 mhz) x tbd ma/mhz = tbd ma. 8. idle idd can be estimated for frequencies < tbd mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate idle for > tbd mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 2.0 v; f = 5 mhz, idle i dd = tbd ma ? (25 mhz ? 5 mhz) x tbd ma/mhz = tbd ma.
C8051F410/1/2/3 38 rev. 0.8 digital supply current?cpu inactive (idle mode, not fetching instructions from flash) core supply current (i dd ) (note 5) v dd = 2.0 v: f = 32 khz f = 1 mhz f = 25 mhz f = 50 mhz v dd = 2.5 v: f = 32 khz f = 1 mhz f = 25 mhz f = 50 mhz ? ? ? ? ? ? ? ? 10 0.15 2.8 5 11 0.21 3.8 7.5 tbd tbd ? tbd tbd tbd ? tbd a ma ma ma a ma ma ma supply sensitivity (i dd ) (notes 5 and 6) f = 25 mhz f = 1 mhz ? ? tbd tbd ? ? %/v %/v frequency sensitivity (i dd ) (notes 5 and 8) v dd = 2.0 v: f < 15 mhz, t = 25 oc f > 15 mhz, t = 25 oc v dd = 2.5 v: f < 15 mhz, t = 25 oc f > 15 mhz, t = 25 oc ? ? ? ? tbd tbd tbd tbd ? ? ? ? ma/mhz ma/mhz ma/mhz ma/mhz digital supply current (suspend mode) oscillator not running, vdd = 2.5 v ? 150 tbd na digital supply current (stop mode, shutdown) oscillator not running, vdd = 2.5 v ? 150 tbd na table 3.1. global dc electrical characteristics (continued) ?40 to +85 c, 50 mhz system clock unless otherwise specified. typical values are given at 25 c parameter conditions min typ max units notes: 1. for more information on v regin characteristics, see table 8.1 on page 82. 2. the backup supply voltage (v rtc-backup ) is used to power the smartclock peripheral only. 3. sysclk is the internal device clock. for operational speeds in excess of 25 mhz, sysclk must be derived from the internal clock multiplier. 4. sysclk must be at least 32 khz to enable debugging. 5. based on device characterization data, not production tested. 6. active and inactive idd at voltages and frequencies other than those specified can be calculated using the idd supply sensitivity. for example, if the v dd is 2.2 v instead of 2.0 v at 25 mhz: i dd = tbd ma typical at 2.0 v and f = 25 mhz. from this, i dd = tbd ma + tbd x (2.2 v ? 2.0 v) = tbd ma at 2.2 v and f = 25 mhz. 7. i dd can be estimated for frequencies < tbd mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate i dd for > tbd mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 2.0 v; f = 20 mhz, i dd = tbd ma ? (25 mhz ? 20 mhz) x tbd ma/mhz = tbd ma. 8. idle idd can be estimated for frequencies < tbd mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. when using these numbers to estimate idle for > tbd mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 2.0 v; f = 5 mhz, idle i dd = tbd ma ? (25 mhz ? 5 mhz) x tbd ma/mhz = tbd ma.
rev. 0.8 39 C8051F410/1/2/3 table 3.2. index to electrical characteristics tables table title page # adc0 electrical characteristics (v dd = 2.5 v, v ref = 2.2 v) 67 adc0 electrical characteristics (v dd = 2.1 v, v ref = 1.5 v) 68 idac electrical characteristics 75 voltage reference electrical characteristics 79 voltage regulator electrical specifications 82 comparator electrical characteristics 92 reset electrical characteristics 134 flash electrical characteristics 143 port i/o dc electrical characteristics 163 oscillator electrical characteristics 175
C8051F410/1/2/3 40 rev. 0.8 n otes :
rev. 0.8 41 C8051F410/1/2/3 4. pinout and package definitions table 4.1. pin definitions fo r the c8051f41x name pin numbers type description ?f410/2 ?f411/3 v dd 7 6 core supply voltage. v io 1 28 i/o supply voltage. gnd 6 5 ground. v rtc-backup 3 2 smartclock backup supply voltage. v regin 8 7 on-chip voltage regulator input. rst / c2ck 2 1 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. a 1 k ? pullup to v dd is recommended. see reset sources section for a complete description. clock signal for the c2 debug interface. p2.7/ c2d 32 27 d i/o d i/o port 2.7. see port i/o section for a complete description. bi-directional data signal for the c2 debug interface. xtal3 5 4 a in smartclock oscillator crystal input. see section 20. "smartclock (real time clock)" for a complete description. xtal4 4 3 a out smartclock oscillator crystal input. see section 20. "smartclock (real time clock)" for a complete description. p0.0/ idac0 17 16 d i/o or a in a out port 0.0. see port i/o section for a complete description. idac0 output. see idac section for complete description. p0.1/ idac1 18 17 d i/o or a in a out port 0.1. see port i/o section for a complete description. idac1 output. see idac section for complete description. p0.2 19 18 d i/o or a in port 0.2. see port i/o section for a complete description. p0.3 20 19 d i/o or a in port 0.3. see port i/o section for a complete description.
C8051F410/1/2/3 42 rev. 0.8 p0.4/ tx 21 20 d i/o or a in d out port 0.4. see port i/o section for a complete description. uart tx pin. see port i/o section for a complete descrip - tion. p0.5/ rx 22 21 d i/o or a in d in port 0.5. see port i/o section for a complete description. uart rx pin. see port i/o section for a complete descrip - tion. p0.6/ cnvstr 23 22 d i/o or a in d in port 0.6. see port i/o section for a complete description. external convert start input for adc0, ida0, and ida1. see adc0 or idacs section for a complete description. p0.7 24 23 d i/o or a in port 0.7. see port i/o section for a complete description. p1.0/ xtal1 9 8 d i/o or a in a in port 1.0. see port i/o section for a complete description. external clock input. this pin is the external oscillator return for a crystal or resonator. see oscillator section. p1.1/ xtal2 10 9 d i/o or a in a o or d in port 1.1. see port i/o section for a complete description. external clock output. this pin is the excitation driver for an external crystal or resonator, or an external clock input for cmos, capacitor, or rc oscillator configurations. see oscillator section. p1.2 v ref 11 10 d i/o or a in a in port 1.2. see port i/o section for a complete description. external v ref input. see v ref section. p1.3 12 11 d i/o or a in port 1.3. see port i/o section for a complete description. p1.4 13 12 d i/o or a in port 1.4. see port i/o section for a complete description. p1.5 14 13 d i/o or a in port 1.5. see port i/o section for a complete description. p1.6 15 14 d i/o or a in port 1.6. see port i/o section for a complete description. table 4.1. pin definitions fo r the c8051f41x (continued) name pin numbers type description ?f410/2 ?f411/3
rev. 0.8 43 C8051F410/1/2/3 p1.7 16 15 d i/o or a in port 1.7. see port i/o section for a complete description. p2.0 25 24 d i/o or a in port 2.0. see port i/o section for a complete description. p2.1 26 25 d i/o or a in port 2.1. see port i/o section for a complete description. p2.2 27 26 d i/o or a in port 2.2. see port i/o section for a complete description. p2.3* 28 d i/o or a in port 2.3. see port i/o section for a complete description. p2.4* 29 d i/o or a in port 2.4. see port i/o section for a complete description. p2.5* 30 d i/o or a in port 2.5. see port i/o section for a complete description. p2.6* 31 d i/o or a in port 2.6. see port i/o section for a complete description. *note: available only on the C8051F410/2. table 4.1. pin definitions fo r the c8051f41x (continued) name pin numbers type description ?f410/2 ?f411/3
C8051F410/1/2/3 44 rev. 0.8 figure 4.1. lqfp-32 pi nout diagram (top view) 1 v rtc-backup p0.7 p0.2 p0.5 / rx p0.6 / cnvstr p0.4 / tx v dd rst/c2ck p0.1 / idac1 p0.0 / idac0 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p0.3 C8051F410/2 top view v regin xtal4 xtal3 v io p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p1.2 / vref p2.3 p2.4 p2.5 p1.1 / xtal2 p1.0 / xtal1 gnd p2.2 p2.6 p2.7 / c2d
rev. 0.8 45 C8051F410/1/2/3 figure 4.2. qfn-28 pinout diagram (top view) 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 c8051f411/3 top view rst / c2ck v rtc-backup xtal4 xtal3 gnd v dd v regin p1.0 / xtal1 p1.1 / xtal2 p1.2 / vref p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 / idac0 p0.1 / idac1 p0.2 p0.3 p0.4 / tx p0.5 / rx p0.6 / cnvstr p0.7 p2.0 p2.1 p2.2 p2.7 / c2d v io gnd gnd
C8051F410/1/2/3 46 rev. 0.8 figure 4.3. lqfp-32 package diagram table 4.2. lqfp-32 package dimensions mm min typ max a- -1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 d-9.00- d1 - 7.00 - e-0.80- e-9.00- e1 - 7.00 - l 0.45 0.60 0.75 pin 1 i dentifier a1 e b 1 32 e1 d1 d e a2 a l
rev. 0.8 47 C8051F410/1/2/3 figure 4.4. qfn-28 package drawing 1 e d a2 a a1 e a3 e2 r e l bottom view side view 2 3 4 5 6 7 8 9 10 12 13 14 21 20 19 17 16 15 28 27 26 24 23 22 e2 25 2 d2 11 18 d2 2 6 x e 6 x e detail 1 detail 1 aa bb cc dd b table 4.3. qfn-28 package dimensions mm min typ max a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 0 0.65 1.00 a3 - 0.25 - b 0.18 0.23 0.30 d-5.00- d2 2.90 3.15 3.35 e-5.00- e2 2.90 3.15 3.35 e-0.5- l 0.45 0.55 0.65 n-28- nd - 7 - ne - 7 - r0.09 - - aa - 0.435 - bb - 0.435 - cc - 0.18 - dd - 0.18 -
C8051F410/1/2/3 48 rev. 0.8 figure 4.5. typical qfn-28 landing diagram optional gnd connection b l 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm e e d 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm top view e2 d2 0.20 mm 0.20 mm 0.50 mm 0.50 mm
rev. 0.8 49 C8051F410/1/2/3 figure 4.6. typical qfn-28 solder paste mask b l 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm e e d 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm top view e2 d2 0.20 mm 0.20 mm 0.50 mm 0.50 mm 0.30 mm 0.20 mm 0.60 mm 0.40 mm 0.70 mm 0.60 mm
C8051F410/1/2/3 50 rev. 0.8 n otes :
rev. 0.8 51 C8051F410/1/2/3 5. 12-bit adc (adc0) the adc0 subsystem for the c8051f41x consists of an analog multiplexer (amux0) with 27 total input selections, and a 200 ksps, 12-bit successive-approximation-register adc with integrated track-and-hold, programmable window detector, and hardware accumulator. the adc0 subsystem has a special burst mode which can automatically enable adc0, capture and accumulate samples, then place adc0 in a low power shutdown mode without cpu intervention. the amux0, data conversion modes, and window detec - tor are all configurable under software control via the special function registers shown in figure 5.1 . adc0 inputs are single-ended and may be configured to measure p0.0-p2.7, the temperature sensor out - put, v dd , or gnd with respect to gnd. adc0 is enabled when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1, or when performing conversions in burst mode. adc0 is in low power shut - down when ad0en is logic 0 and no burst mode conversions are taking place. figure 5.1. adc0 func tional block diagram 5.1. analog multiplexer amux0 selects the input channel to the adc. any of the following may be selected as an input: p0.0-p2.7, the on-chip temperature sensor, the core power supply (v dd ), or ground (gnd). adc0 is single-ended and all signals measured are with respect to gnd. the adc0 input channels are selected using the adc0mx register as described in sfr definition 5.1 . important note about adc0 input configuration: port pins selected as adc0 inputs should be config - ured as analog inputs and should be skipped by the digital crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register pnmdin (for n = 0,1,2) and write a ?1? in the corresponding port latch register pn (for n = 0,1,2). to force the crossbar to skip a port pin, set to ?1? the corresponding bit in register pnskip (for n = 0,1,2). see section ?18. port input/output? on page 147 for more port i/o configuration details. 12-bit sar adc ref fclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0ljst ad0wint ad0busy ad0int bursten ad0en timer 2 overflow start conversion 00 ad0busy (w) vdd adc0lth ad0wint 27-to-1 amux vdd p0.0 p0.7 01 10 11 cnvstr input window compare logic p1.0 p1.7 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l adc0mx adc0mx4 adc0mx3 adc0mx2 adc0mx1 adc0mx0 p2.0 p2.3-p2.6 available on ?f410/2 p2.7 gnd temp sensor adc0cf ad0rpt0 ad0rpt1 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 adc0tk ad0pwr3 ad0pwr2 ad0pwr1 ad0pwr0 ad0tm1 ad0tm0 ad0tk1 ad0tk0 burst mode logic ad0post ad0pre ad0tm1:0 accumulator start conversion burst mode oscillator 25 mhz max sysclk fclk
C8051F410/1/2/3 52 rev. 0.8 5.2. temperature sensor the typical temperature sensor transfer function is shown in figure 5.2. the output voltage (v temp ) is the positive adc input when the temperature sensor is selected by bits ad0mx4-0 in register adc0mx. figure 5.2. typical temperatur e sensor transfer function 5.3. adc0 operation in a typical system, adc0 is configured using the following steps: step 1. choose the start of conversion source. step 2. choose normal mode or burst mode operation. step 3. if burst mode, choose the adc0 idle power state and set the power-up time. step 4. choose the tracking mode. note that pre-tracking mode can only be used with normal mode. step 5. calculate required settling time and set the post convert-start tracking time using the ad0tk bits. step 6. choose the repeat count. step 7. choose the output word justification (right-justified or left-justified). step 8. enable or disable the end of conversion and window comparator interrupts. 0 -50 50 100 (celsiu s) 0 .500 0 .600 0 .700 0 .800 0 .900 ( volts) v temp = slope(temp c ) + offset 1 .000
rev. 0.8 53 C8051F410/1/2/3 5.3.1. starting a conversion a conversion can be initiated in one of four ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm1-0) in register adc0cn. conversions may be initiated by one of the fol - lowing: writing a ?1? to the ad0busy bit of register adc0cn a timer 3 overflow (i.e., timed continuous conversions) a rising edge on the cnvstr input signal (pin p0.6) a timer 2 overflow (i.e., timed continuous conversions) writing a ?1? to ad0busy provides software control of adc0 whereby conversions are performed "on- demand.? during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0busy triggers an interrupt (when enabled) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion completions, the adc0 interrupt flag (ad0int) should be used. converted data is available in the adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2 or timer 3 overflows are used as the conversion source, low byte over - flows are used if timer 2/3 is in 8-bit mode; high byte overflows are used if timer 2/3 is in 16-bit mode. see section ?24. timers? on page 231 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0.6, set bit 6 in the p0skip register to logic 1. see section ?18. port input/output? on page 147 for details on port i/o configuration. 5.3.2. tracking modes according to table 5.3 and table 5.4, each adc0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. adc0 has three tracking modes: pre-tracking, post-tracking, and dual-tracking. pre-tracking mode provides the minimum delay between the convert start signal and end of conversion by tracking continuously before the convert start signal. this mode requires software management in order to meet minimum tracking requirements. in post-tracking mode, a programmable tracking time starts after the convert start signal and is managed by hardware. dual-tracking mode maxi - mizes tracking time by tracking before and after the convert start signal. figure 5.3 shows examples of the three tracking modes. pre-tracking mode is selected when ad0tm is set to 10b. conversions are started immediately following the convert start signal. adc0 is tracking continuously when not performing a conversion. software must allow at least the minimum tracking time between each end of conversion and the next convert start signal. the minimum tracking time must also be met prior to the first convert start signal after adc0 is enabled. post-tracking mode is selected when ad0tm is set to 01b. a programmable tracking time based on ad0tk is started immediately following the convert start signal. conversions are started after the pro - grammed tracking time ends. after a conversion is complete, adc0 does not track the input. rather, the sampling capacitor remains disconnected from the input making the input pin high-impedance until the next convert start signal. dual-tracking mode is selected when ad0tm is set to 11b. a programmable tracking time based on ad0tk is started immediately following the convert start signal. conversions are started after the pro - grammed tracking time ends. after a conversion is complete, adc0 tracks continuously until the next con - version is started.
C8051F410/1/2/3 54 rev. 0.8 depending on the output connected to the adc input, additional tracking time, more than is specified in ta b l e 5.3 and table 5.4 , may be required after changing mux settings. see the settling time requirements described in section ?5.3.6. settling time requirements? on page 58 . figure 5.3. adc0 tracking modes 5.3.3. timing adc0 has a maximum conversion speed specified in table 5.3 and table 5.4. adc0 is clocked from the adc0 subsystem clock (fclk). the source of fclk is selected based on the bursten bit. when bursten is logic 0, fclk is derived from the current system clock. when bursten is logic 1, fclk is derived from the burst mode oscillator, an independent clock source with a maximum frequency of 25 mhz. when adc0 is performing a conversion, it requires a clock source that is typically slower than fclk. the adc0 sar conversion clock (sar clock) is a divided version of fclk. the divide ratio can be configured using the ad0sc bits in the adc0cf register. the maximum sar clock frequency is listed in table 5.3 and table 5.4 . adc0 can be in one of three states at any given time: tracking, converting, or idle. tracking time depends on the tracking mode selected. for pre-tracking mode, tracking is managed by software and adc0 starts conversions immediately following the convert start signal. for post-tracking and dual-tracking modes, the tracking time after the convert start signal is equal to the value determined by the ad0tk bits plus 2 fclk cycles. tracking is immediately followed by a conversion. the adc0 conversion time is always 13 sar clock cycles plus an additional 2 fclk cycles to start and complete a conversion. figure 5.4 shows timing diagrams for a conversion in pre-tracking mode and tracking plus conversion in post-tracking or dual-tracking mode. in this example, repeat count is set to one. convert start p ost-tracking ad0tm= 01 track convert idle idle track convert. . pre-tracking ad0tm = 10 track convert track convert ... d ual-tracking ad0tm = 11 track convert track track track convert. .
rev. 0.8 55 C8051F410/1/2/3 figure 5.4. 12-bit adc tracking mode example c onvert start adc0 state track adc0 state convert time f s1 s2 s12 s13 ... f time f s1 s2 s12 s13 ... f convert f s1 s2 f post-tracking or dual-tracking modes (ad0tk = ?00') pre-tracking mode ad0int flag ad0int flag key f s n equal to one period of fclk. each sn is equal to one period of the sar clock.
C8051F410/1/2/3 56 rev. 0.8 5.3.4. burst mode burst mode is a power saving feature that allows adc0 to remain in a low power state between conver - sions. when burst mode is enabled, adc0 wakes from a low power state, accumulates 1, 4, 8, or 16 sam - ples using an internal burst mode clock (approximately 25 mhz), then re-enters a low power state. since the burst mode clock is independent of the system clock, adc0 can perform multiple conversions then enter a low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 khz), or suspended. burst mode is enabled by setting bursten to logic 1. when in burst mode, ad0en controls the adc0 idle power state (i.e. the state adc0 enters when not tracking or performing conversions). if ad0en is set to logic 0, adc0 is powered down after each burst. if ad0en is set to logic 1, adc0 remains enabled after each burst. on each convert start signal, adc0 is awakened from its idle power state. if adc0 is powered down, it will automatically power up and wait the programmable power-up time controlled by the ad0pwr bits. otherwise, adc0 will start tracking and converting immediately. figure 5.5 shows an exam - ple of burst mode operation with a slow system clock and a repeat count of 4. important note: when burst mode is enabled, only post-tracking and dual-tracking modes can be used. when burst mode is enabled, a single convert start will initiate a number of conversions equal to the repeat count. when burst mode is disabled, a convert start is required to initiate each conversion. in both modes, the adc0 end of conversion interrupt flag (ad0int) will be set after ?repeat count? conversions have been accumulated. similarly, the window comparator will not compare the result to the greater-than and less-than registers until ?repeat count? conversions have been accumulated. note: when using burst mode, care must be taken to issue a convert start signal no faster than once every four sysclk periods. this includes external convert start signals. figure 5.5. 12-bit adc burst mode example with repeat count set to 4 convert start post-tracking ad0tm = 01 ad0en = 0 powered down powered down system clock t c power-up and idle t c t c t c power-up and idle t c.. d ual-tracking ad0tm = 11 ad0en = 0 powered down powered down t c power-up and track t c t c t c power-up and track t c.. ad0pwr post-tracking ad0tm = 01 ad0en = 1 idle idle t c t c t c t c t c.. d ual-tracking ad0tm = 11 ad0en = 1 track track t c t c t c t c t c.. t c t c t c t c t = tracking c = converting
rev. 0.8 57 C8051F410/1/2/3 5.3.5. output conversion code the registers adc0h and adc0l contain the high and low bytes of the output conversion code. when the repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output conversion code is updated after each conversion. inputs are measured from ?0? to v ref x 4095/4096. data can be right-justified or left-justified, depending on the setting of the ad0ljst bit (adc0cn.2). unused bits in the adc0h and adc0l registers are set to ?0?. example codes are shown in table 5.1 for both right-justified and left-justified data. when the adc0 repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions performed and is updated after the last conversion in the series is finished. sets of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. the repeat count can be selected using the ad0rpt bits in the adc0cf register. the value must be right- justified (ad0ljst = ?0?), and unused bits in the adc0h and adc0l registers are set to '0'. the example in table 5.2 shows the right-justified result for various input voltages and repeat counts. notice that accumulating 2 n samples is equivalent to left-shifting by n bit positions when all samples returned from the adc have the same value. table 5.1. adc0 examples of right- a nd left-justified samples input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) v ref x 4095/4096 0x0fff 0xfff0 v ref x 2048/4096 0x0800 0x8000 v ref x 2047/4096 0x07ff 0x7ff0 0 0x0000 0x0000 table 5.2. adc0 repeat count examples at various input voltages input voltage repeat count = 4 repeat count = 8 repeat count = 16 v ref x 4095/4096 0x3ffc 0x7ff8 0xfff0 v ref x 2048/4096 0x2000 0x4000 0x8000 v ref x 2047/4096 0x1ffc 0x3ff8 0x7ff0 0 0x0000 0x0000 0x0000
C8051F410/1/2/3 58 rev. 0.8 5.3.6. settling time requirements a minimum tracking time is required before an accurate conversion can be performed. this tracking time is determined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. figure 5.6 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1 . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b le 5.3 and ta b l e 5.4 for adc0 minimum set - tling time requirements. equation 5.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (12). figure 5.6. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ln = r mux = tbd c sample = 12 p f rc input = r mux * c sample mux select px.x
rev. 0.8 59 C8051F410/1/2/3 sfr definition 5.1. adc0mx: adc0 channel select bits7-5: unused. read = 000b; write = don?t care. bits4-0: ad0mx4-0: amux0 positive input selection *note: only applies to C8051F410/2; selection reserved on c8051f411/3 devices. r r r r/w r/w r/w r/w r/w reset value - - - ad0mx 00011111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb ad0mx4-0 adc0 input channel 00000 p0.0 00001 p0.1 00010 p0.2 00011 p0.3 00100 p0.4 00101 p0.5 00110 p0.6 00111 p0.7 01000 p1.0 01001 p1.1 01010 p1.2 01011 p1.3 01100 p1.4 01101 p1.5 01110 p1.6 01111 p1.7 10000 p2.0 10001 p2.1 10010 p2.2 10011 p2.3* 10100 p2.4* 10101 p2.5* 10110 p2.6* 10111 p2.7 11000 temp sensor 11001 v dd 11010 - 11111 gnd
C8051F410/1/2/3 60 rev. 0.8 sfr definition 5.2. adc0cf: adc0 configuration bits7-3: ad0sc4-0: adc0 sar conversion clock period bits. sar conversion clock is derived from fclk by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4-0. sar conversion clock requirements are given in table 5.3. bursten = 0: fclk is the current system clock. bursten = 1: fclk is a maximum of 25 mhz, independent of the current system clock. * or *note: round the result up. bits2-1: ad0rpt1-0: adc0 repeat count. controls the number of conversions taken and accumulated between adc0 end of conversion (adcint) and adc0 window comparator (adcwint) interrupts. a convert start is required for each conversion unless burst mode is enabled. in burst mode, a single convert start can initiate multiple self-timed conversions. results in both modes are accumulated in the adc0h:adc0l register. when ad0rpt1-0 are set to a value other than '00', the ad0ljst bit in the adc0cn regist er must be set to '0' (right justified). 00: 1 conversion is performed. 01: 4 conversions are performed and accumulated. 10: 8 conversions are performed and accumulated. 11: 16 conversions are performed and accumulated. bit0: reserved. read = 0b; must write 0b. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc ad0rpt reserved 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc ad0sc fclk clk sar -------------------- 1 ? = clk sar fclk ad 0 sc 1 + ---------------------------- =
rev. 0.8 61 C8051F410/1/2/3 sfr definition 5.3. adc0h: adc0 data word msb sfr definition 5.4. adc0l: adc0 data word lsb bits7-0: adc0 data word high-order bits. for ad0ljst = 0 and ad0rpt as follows: 00: bits 3?0 are the upper 4 bits of the accumulated result. bits 7?4 are 0000b. 01: bits 5?0 are the upper 6 bits of the accumulated result. bits 7?6 are 00b. 10: bits 6?0 are the upper 7 bits of the accumulated result. bit 7 is 0b. 11: bits 7?0 are the upper 8 bits of the accumulated result. for ad0ljst = 1 (ad0rpt must be '00'): bits 7?0 are the most-significant bits of the adc0 12-bit result. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe bits7-0: adc0 data word low-order bits. for ad0ljst = 0: bits 7-0 are the lower 8 bits of the adc0 accumulated result. for ad0ljst = 1 (ad0rpt must be '00'): bits 7-4 are the lower 4 bits of the 12-bit result. bits 3-0 are 0000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbd
C8051F410/1/2/3 62 rev. 0.8 sfr definition 5.5. adc0cn: adc0 control bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: bursten: adc0 burst mode enable bit. 0: adc0 burst mode disabled. 1: adc0 burst mode enabled. bit5: ad0int: adc0 conversion complete interrupt flag. 0: adc0 has not completed a data conversion since the last time ad0int was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm1-0 = 00b bit3: ad0wint: adc0 window compare interrupt flag. this bit must be cleared by software. 0: adc0 window comparison data match has not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bit2: ad0ljst: adc0 left justify select 0: data in adc0h:adc0l registers is right justified. 1: data in adc0h:adc0l registers is left justified. this option should not be used with a repeat count greater than 1 (when ad0rpt1-0 is 01b, 10b, or 11b). bits1-0: ad0cm1-0: adc0 start of conversion mode select. 00: adc0 conversion initiated on every write of ?1? to ad0busy. 01: adc0 conversion initiated on overflow of timer 3. 10: adc0 conversion initiated on rising edge of external cnvstr. 11: adc0 conversion initiated on overflow of timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en bursten ad0int ad0busy ad0wint ad0ljst ad0cm1 ad0cm0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8
rev. 0.8 63 C8051F410/1/2/3 sfr definition 5.6. adc0tk: adc0 tracking mode select 5.4. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro - grammed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) reg - isters hold the comparison values. the window detector flag can be programmed to indicate when mea - sured data is inside or outside of the user-programmed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. bits7-4: ad0pwr3-0: adc0 burst power-up time. for bursten = 0: adc0 power state controlled by ad0en. for bursten = 1 and ad0en = 1; adc0 remains enabled and does not enter the low power state. for bursten = 1 and ad0en = 0: adc0 enters the low power state as specified in table 5.3 and table 5.4 and is enabled after each convert start signal. the power up time is programmed according to the following equation: or bits3-2: ad0tm1-0: adc0 tracking mode select bits. 00: reserved. 01: adc0 is configured to post-tracking mode. 10: adc0 is configured to pre-tracking mode. 11: adc0 is configured to dual-tracking mode (default). bits1-0: ad0tk1-0: adc0 post-track time. post-tracking time is controlled by ad0tk as follows: 00: post-tracking time is equal to 2 sar clock cycles + 2 fclk cycles. 01: post-tracking time is equal to 4 sar clock cycles + 2 fclk cycles. 10: post-tracking time is equal to 8 sar clock cycles + 2 fclk cycles. 11: post-tracking time is equal to 16 sar clock cycles + 2 fclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0pwr ad0tm ad0tk 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xba ad0pwr tstartup 200 ns ---------------------- 1 ? = tstartup ad0pwr 1 + () 200 n s =
C8051F410/1/2/3 64 rev. 0.8 sfr definition 5.7. adc0gth: adc0 greater-than data high byte sfr definition 5.8. adc0gtl: adc0 greater-than data low byte bits7-0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 bits7-0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc3
rev. 0.8 65 C8051F410/1/2/3 sfr definition 5.9. adc0lth: adc0 less-than data high byte sfr definition 5.10. adc0ltl: adc0 less-than data low byte bits7-0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6 bits7-0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc5
C8051F410/1/2/3 66 rev. 0.8 5.4.1. window detector in single-ended mode figure 5.7 shows two example window comparisons for right-justified data with adc0lth:adc0ltl = 0x0200 (512d) and adc0gth:adc0gtl = 0x0100 (256d). the input voltage can range from ?0? to v ref x (4095/4096) with respect to gnd, and is represented by a 12-bit unsigned integer value. the repeat count is set to one. in the left example, an ad0wint interrupt will be generated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0100 < adc0h:adc0l < 0x0200). in the right example, and ad0wint interrupt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0100 or adc0h:adc0l > 0x0200). figure 5.8 shows an exam - ple using left-justified data with the same comparison values. figure 5.7. adc window compare example: right-justified single-ended data figure 5.8. adc window compare exampl e: left-justified single-ended data 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 0 input voltage (px.x - gnd) vref x (4095/4096) vref x (512/4096) vref x (256/4096) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 0 input voltage (px.x - gnd) vref x (4095/ 4096) vref x (512/4096) vref x (256/4096) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 0 input voltage (px.x - gnd) vref x (4095/4096) vref x (512/4096) vref x (256/4096) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 0 input voltage (px.x - gnd) vref x (4095/4096) vref x (512/4096) vref x (256/4096) ad0wint not affected ad0wint= 1 ad0wint= 1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
rev. 0.8 67 C8051F410/1/2/3 table 5.3. adc0 electrical characteristics (v dd = 2.5 v, v ref = 2.2 v) v dd = 2.5 v, v ref = 2.2 v (refsl=0), ?40 to +85 c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity ? ? 1 lsb differential nonlinearity guaranteed monotonic ? ? 1 lsb offset error ? 1 tbd lsb full scale error ? 1 tbd lsb dynamic performance (10 khz sine-wave single-ended input, 0 to 1 db below full scale, 200 ksps) signal-to-noise plus distortion 66 69 ? db total harmonic distortion up to the 5 th harmonic ? ?77 ? db spurious-free dynamic range ? ?94 ? db conversion rate sar conversion clock ? ? 10 mhz conversion time in sar clocks note 1 ? 13 ? clocks track/hold acquisition time note 2 1 ? ? s throughput rate ? ? 200 ksps analog inputs input voltage range 0 ? v ref v input capacitance ? 12 ? pf temperature sensor linearity notes 3, 4 ? tbd ? c slope note 4 ? 2.95 ? mv/c slope error note 3 ? 73 ? v/c offset note 4 (temp = 0 c) ? 900 ? mv offset error note 3 ? 17 ? mv power specifications power supply current (v dd supplied to adc0) operating mode, 200 ksps ? 680 tbd a burst mode (idle) ? 100 ? a power supply rejection ? 1 ? mv/v notes: 1. an additional 2 fclk cycles are required to start and complete a conversion. 2. additional tracking time may be required depending on the output impedance connected to the adc input. see section ? 5.3.6. settling time requirements ? on page 58 . 3. represents one standard deviation from the mean. 4. includes adc offset, gain, and linearity variations.
C8051F410/1/2/3 68 rev. 0.8 table 5.4. adc0 electrical characteristics (v dd = 2.1 v, v ref = 1.5 v) v dd = 2.1 v, v ref = 1.5 v (refsl = 0), ?40 to +85 c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity ? ? 1 lsb differential nonlinearity guaranteed monotonic ? ? 1 lsb offset error ? 1 tbd lsb full scale error ? 1 tbd lsb dynamic performance (10 khz sine-wave single-ended input, 0 to 1 db below full scale, 200 ksps) signal-to-noise plus distortion 66 68 ? db total harmonic distortion up to the 5 th harmonic ? ?75 ? db spurious-free dynamic range ? ?90 ? db conversion rate sar conversion clock ? ? 10 mhz conversion time in sar clocks note 1 ? 13 ? clocks track/hold acquisition time note 2 1 ? ? s throughput rate ? ? 200 ksps analog inputs input voltage range 0 ? v ref v input capacitance ? 12 ? pf temperature sensor linearity notes 3, 4 ? tbd ? c slope note 4 ? 2.95 ? mv/c slope error note 3 ? 73 ? v/c offset note 4 (temp = 0 c) ? 900 ? mv offset error note 3 ? 17 ? mv power specifications power supply current (v dd sup - plied to adc0) operating mode, 200 ksps ? 650 tbd a burst mode (idle) ? 100 ? a power supply rejection ? 1 ? mv/v notes: 1. an additional 2 fclk cycles are required to start and complete a conversion. 2. additional tracking time may be required depending on the output impedance connected to the adc input. see section ? 5.3.6. settling time requirements ? on page 58 . 3. represents one standard deviation from the mean. 4. includes adc offset, gain, and linearity variations.
rev. 0.8 69 C8051F410/1/2/3 6. 12-bit current mode dacs (ida0 and ida1) the c8051f41x devices include two 12-bit current-mode digital-to-analog converters (idacs). the maxi - mum current output of the idacs can be adjusted for four different current settings; 0.25 ma, 0.5 ma, 1 ma, and 2 ma. the idacs can be individually enabled or disabled using the enable bits in the corre - sponding idac control register (ida0cn or ida1cn). when both idacs are enabled, their outputs may be routed to individual pins or merged onto a single pin. an internal bandgap bias generator is used to gen - erate a reference current for the idacs whenever they are enabled. idac updates can be performed on- demand, scheduled on a timer overflow, or synchronized with an external pin edge. figure 6.1 shows a block diagram of the idac circuitry. figure 6.1. idac functional block diagram 6.1. idac output scheduling a flexible output update mechanism allows for seamless full-scale changes and supports jitter-free updates for waveform generation. three update modes are provided, allowing idac output updates on a write to the idac?s data register, on a timer overflow, or on an external pin edge. 6.1.1. update output on-demand in its default mode (idancn.[6:4] = ?111?) the idac output is updated ?on-demand? with a write to the data register high byte (idanh). it is important to note that in this mode, writes to the data register low byte (idanl) are held and have no effect on the idan output until a write to idanh takes place. since data from both the high and low bytes of the data register are immediately latched to idan after a write to idanh, the write sequence when writing a full 12-bit word to the idac data registers should be idanl followed by idanh . when the data word is left justified, the idac can be used in 8-bit mode by initializing idanl to the desired value (typically 0x00), and writing data only to ida0h. idan 12 idan outp ut idancn idanen idancm2 idancm1 idancm0 idanrjst idanomd1 idanomd0 idanh latch 8 idanh timer 0 timer 1 timer 2 timer 3 cnvstr idanl 4
C8051F410/1/2/3 70 rev. 0.8 6.1.2. update output based on timer overflow the idac output update can be scheduled on a timer overflow. this feature is useful in systems where the idac is used to generate a waveform of a defined sampling rate, by eliminating the effects of variable interrupt latency and instruction execution on the timing of the idac output. when the idancm bits (idancn.[6:4]) are set to ?000?, ?001?, ?010? or ?011?, writes to both idac data registers (idanl and idanh) are held until an associated timer overflow event (timer 0, timer 1, timer 2 or timer 3, respectively) occurs, at which time the idanh:idanl contents are copied to the idac input latch, allowing the idac out - put to change to the new value. when updates are scheduled based on timer 2 or 3, updates occur on low-byte overflows if timer 2 or 3 is in 8-bit mode and high-byte overflows if timer 2 or 3 is in 16-bit mode. 6.1.3. update output based on cnvstr edge the idac output can also be configured to update on a rising edge, falling edge, or both edges of the external cnvstr signal. when the idancm bits (idancn.[6:4]) are set to ?100?, ?101?, or ?110?, writes to the idac data registers (idanl and idanh) are held until an edge occurs on the cnvstr input pin. the particular setting of the idancm bits determines whether the idac output is updated on rising, falling, or both edges of cnvstr. when a corresponding edge occurs, the idanh:idanl contents are copied to the idac input latch, allowing the idac output to change to the new value. 6.2. idac output mapping the idac data word can be left justified or right justified as shown in figure 6.2. when left justified, the 8 msbs of the data word (d11-d4) are mapped to bits 7-0 of the idanh register and the 4 lsbs of the data word (d3-d0) are mapped to bits 7-4 of the idanl register. when right justified, the 4 msbs of the data word (d11-d8) are mapped to bits 3-0 of the idanh register and the 8 lsbs of the data word (d7-d0) are mapped to bits 7-0 of the idanl register. the idac data word justification is selected using the idanrjst bit (idancn.2). the full-scale output current of the idac is selected using the idanomd bits (idancn[1:0]). by default, the idac is set to a full-scale output current of 2 ma. the idanomd bits can also be configured to provide full-scale output currents of 0.25 ma, 0.5 ma, or 1 ma. figure 6.2. idac data word mapping left justified data (idanrjst = 0): right justified data (idanrjst = 1): idanh idanl d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idanh idanl d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idan data word (d11 - d0) output current vs idanomd bit setting ?11? (2 ma) ?10? (1 ma) ?01? (0.5 ma) ?00? (0.25 ma) 0x000 0 ma 0 ma 0 ma 0 ma 0x001 1/4096 x 2 ma 1/4096 x 1 ma 1/4096 x 0.5 ma 1/4096 x 0.25 ma 0x800 2048/4096 x 2 ma 2048/4096 x 1 ma 2048/4096 x 0.5 ma 2048/4096 x 0.25 ma 0xfff 4095/4096 x 2 ma 4095/4096 x 1 ma 4095/4096 x 0.5 ma 4095/4096 x 0.25 ma
rev. 0.8 71 C8051F410/1/2/3 sfr definition 6.1. ida0cn: ida0 control sfr definition 6.2. ida0h: ida0 data high byte bit 7: ida0en: ida0 enable bit. 0: ida0 disabled. 1: ida0 enabled. bits 6?4: ida0cm[2:0]: ida0 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida0h. bit 3: reserved. read = 0b, write = 0b. bit 2: ida0rjst: ida0 right justify select bit. 0: ida0 data in ida0h:ida0l is left justified. 1: ida0 data in ida0h:ida0l is right justified. bits 1:0: ida0omd[1:0]: ida0 output mode select bits. 00: 0.25 ma full-scale output current. 01: 0.5 ma full-scale output current. 10: 1.0 ma full-scale output current. 11: 2.0 ma full-scale output current. r/w r/w r/w r/w r/w r r/w r/w reset value ida0en ida0cm - ida0rjst ida0omd 01110011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb9 bits 7?0: ida0 data word high-order bits. for ida0rjst = 0: bits 7-0 hold the most significant 8-bits of the 12-bit ida0 data word. for ida0rjst = 1: bits 3-0 hold the most significant 4-bits of the 12-bit ida0 data word. bits 7-4 are 0000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x97
C8051F410/1/2/3 72 rev. 0.8 sfr definition 6.3. ida0l: ida0 data low byte sfr definition 6.4. ida1cn: ida1 control bits 7?0: ida0 data word low-order bits. for ida0rjst = 0: bits 7-4 hold the least significant 4-bits of the 12-bit ida0 data word. bits 3?0 are 0000b. for ida0rjst = 1: bits 7?0 hold the least significant 8-bits of the 12-bit ida0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x96 bit 7: ida1en: ida0 enable bit. 0: ida1 disabled. 1: ida1 enabled. bits 6?4: ida1cm[2:0]: ida1 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida1h. bit 3: reserved. read = 0b, write = 0b. bit 2: ida1rjst: ida1 right justify select bit. 0: ida1 data in ida1h:ida1l is left justified. 1: ida1 data in ida1h:ida1l is right justified. bits 1?0: ida1omd[1:0]: ida1 output mode select bits. 00: 0.25 ma full-scale output current. 01: 0.5 ma full-scale output current. 10: 1.0 ma full-scale output current. 11: 2.0 ma full-scale output current. r/w r/w r/w r/w r/w r r/w r/w reset value ida1en ida1cm - ida1rjst ida1omd 01110011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb5
rev. 0.8 73 C8051F410/1/2/3 sfr definition 6.5. ida1h: ida0 data high byte sfr definition 6.6. ida1l: ida1 data low byte 6.3. idac external pin connections the ida0 output is connected to p0.0, and the ida1 output can be connected to p0.0 or p0.1. the output pin for ida1 is selected using idamrg (ref0cn.7). when the enable bits for both idacs (idanen) are set to ?0?, the idac outputs behave as a normal gpio pins. when either idac?s enable bit is set to ?1?, the digital output drivers and weak pullup for the selected idac pin are automatically disabled, and the pin is connected to the idac output. when using the idacs, the selected idac pin(s) should be skipped in the crossbar by setting the corresponding pnskip bits to a ?1?. figure 6.3 shows the pin connections for ida0 and ida1. when both idacs are enabled and idamrg is set to logic 1, the output of both idacs is merged onto p0.0. bits 7?0: ida1 data word high-order bits. for ida0rjst = 0: bits 7-0 hold the most significant 8-bits of the 12-bit ida1 data word. for ida0rjst = 1: bits 3-0 hold the most significant 4-bits of the 12-bit ida1 data word. bits 7?4 are 0000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf5 bits 7?0: ida1 data word low-order bits. for ida0rjst = 0: bits 7-4 hold the least significant 4-bits of the 12-bit ida1 data word. bits 3?0 are 0000b. for ida0rjst = 1: bits 7?0 hold the least significant 8-bits of the 12-bit ida1 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf4
C8051F410/1/2/3 74 rev. 0.8 figure 6.3. idac pin connections ida0 p0 .0 0 1 ida0en ida1 p0 .1 0 1 ida1en 1 0 idamrg
rev. 0.8 75 C8051F410/1/2/3 . table 6.1. idac electrical characteristics ?40 to +85 c, v dd = 2.0 v full-scale output current set to 2 ma unless otherwise specified. parameter conditions min typ max units static performance resolution 12 bits integral nonlinearity ? ? 10 lsb differential nonlinearity guaranteed monotonic ? ? 1 lsb output compliance range guaranteed by design ? ? v dd ? 1.2 v output noise i out = tbd; r load = tbd ? tbd ? pa/rthz offset error ? 0 ? lsb gain error 2 ma full scale output current ? 0.05 2 % gain-error tempco ? 320 ? na/c v dd power supply rejection ratio ? 2 ? a/v output capacitance ? 2 ? pf dynamic performance startup time ? 10 ? s gain variation from 2 ma range 1 ma full scale output current 0.5 ma full scale output current 0.25 ma full scale output current ? 0.5 0.5 0.5 ? % % % power consumption power supply current 2 ma full scale output current 1 ma full scale output current 0.5 ma full scale output current 0.25 ma full scale output current ? 2.1 1.1 0.6 0.35 ? ma ma ma ma
C8051F410/1/2/3 76 rev. 0.8 n otes :
rev. 0.8 77 C8051F410/1/2/3 7. voltage reference the voltage reference mux on c8051f41x devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the v dd power supply voltage (see figure 7.1 ). the refsl bit in the reference control register (ref0cn) selects the reference source. for an external source or the internal reference, refsl should be set to ?0?. to use v dd as the reference source, refsl should be set to ?1?. the internal voltage reference circuit consists of a temperature stable bandgap voltage reference genera - tor and a gain-of-two output buffer amplifier. the output voltage is selected between 1.5 v and 2.2 v. the internal voltage reference can be driven out on the v ref pin by setting the refbe bit in register ref0cn to a ?1? (see figure 7.1 ). the load seen by the v ref pin must draw less than 200 a to gnd. when using the internal voltage reference, bypass capacitors of 0.1 f and 4.7 f are recommended from the v ref pin to gnd. if the internal reference is not used, the refbe bit should be cleared to ?0?. the biase bit enables the internal voltage bias generator, which is used by the adc, temperature sensor, internal oscillators, and idacs. this bit is forced to logic 1 when any of the aforementioned peripherals are enabled. the bias generator may be enabled manually by writing a ?1? to the biase bit in register ref0cn; see sfr definition 7.1 for ref0cn register details. the electrical specifications for the voltage reference circuit are given in table 7.1. figure 7.1. voltage refere nce functional bl ock diagram reflv reflv
C8051F410/1/2/3 78 rev. 0.8 important note about the v ref pin: port pin p1.2 is used as the external v ref input and as an output for the internal v ref . when using either an external voltage reference or the internal reference circuitry, p1.2 should be configured as an analog pin, and skipped by the digital crossbar. to configure p1.2 as an ana - log pin, clear bit 2 in register p1mdin to ?0? and set bit 2 in register p1 to '1'. to configure the crossbar to skip p1.2, set bit 2 in register p1skip to ?1?. refer to section ?18. port input/output? on page 147 for complete port i/o configuration details. the tempe bit in register ref0cn enables/disables the tempera - ture sensor. while disabled, the temperature sensor defaults to a high impedance state and any adc0 measurements performed on the sensor result in meaningless data. sfr definition 7.1. ref0cn: reference control bit7: idamrg: idac output merge select. 0: ida1 output is p0.1. 1: ida1 output is p0.0 (merged with ida0 output). bit6: gf. general purpose flag. this bit is a general purpose flag for use under software control. bit5: ztcen: zero-tempco bias enable bit. 0: zerotc bias generator automatically enabled when needed. 1: zerotc bias generator forced on. bit4: reflv: voltage reference output level select. this bit selects the output voltage level for the internal voltage reference. 0: internal voltage reference set to 1.5 v. 1: internal voltage reference set to 2.2 v. bit3: refsl: voltage reference select. this bit selects the source for the internal voltage reference. 0: v ref pin used as voltage reference. 1: v dd used as voltage reference. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: internal analog bias generator enable bit. 0: internal analog bias generator automatically enabled when needed. 1: internal analog bias generator on. bit0: refbe: internal reference buffer enable bit. 0: internal reference buffer disabled. 1: internal reference buffer enabled. internal voltage reference driven on the v ref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value idamrg gf ztcen reflv refsl tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1
rev. 0.8 79 C8051F410/1/2/3 table 7.1. voltage reference electrical characteristics v dd = 2.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient (reflv = 0) 25 c ambient (reflv = 1), v dd = 2.5 v 1.47 2.16 1.5 2.2 1.53 2.24 v v ref short-circuit current ? 3.0 ? ma v ref temperature coefficient ? 35 ? ppm/c load regulation load = 0 to 200 a to gnd ? 10 ? ppm/a v ref turn-on time v dd = 2.5 v, v ref = 1.5 v: 4.7 f tantalum, 0.1 f ceramic bypass 0.1 f ceramic bypass v dd = 2.5 v, v ref = 2.2 v: 4.7 f tantalum, 0.1 f ceramic bypass 0.1 f ceramic bypass ? ? ? ? 2.5 55 6.8 144 ? ? ? ? ms s ms s power supply rejection ? 2 ? mv/v external reference (refbe = 0) input voltage range 0 ? v dd v input current sample rate = 200 ksps; v ref = 2 v ? 5 ? a bias generators adc bias generator biase = ?1? ? 22 ? a power consumption (internal) ? 50 ? a
C8051F410/1/2/3 80 rev. 0.8 n otes :
rev. 0.8 81 C8051F410/1/2/3 8. voltage regulator (reg0) c8051f41x devices include an on-chip low dropout voltage regulator (reg0). the input to reg0 at the v regin pin can be as high as 5.25 v. the output can be selected by software to 2.1 v or 2.5 v. when enabled, the output of reg0 appears on the v dd pin, powers the microcontroller core, and can be used to power external devices. on reset, reg0 is enabled and can be disabled by software. the input (v regin ) and output (v dd ) of the voltage regulator should both be protected with a large capaci - tor (4.7 f + 0.1 f) to ground. this capacitor will eliminate power spikes and provide any immediate power required by the microcontroller. a settling time associated with the voltage regulator is shown in ta b l e 8.1 . figure 8.1. external capacitors for voltage regulator input/output if the internal voltage regulator is not used, the v regin input should be tied to v dd , as shown in figure 8.2. figure 8.2. external capacitors for voltage regulator input/output v dd v dd r eg0 4.7 f 4.7 f .1 f .1 f v regi n v regi n v dd v dd 4.7 f .1 f
C8051F410/1/2/3 82 rev. 0.8 sfr definition 8.1. reg0cn: regulator control table 8.1. voltage regulator electrical specifications v dd = 2.1 or 2.5 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range (v regin )* 2.15* ? 5.25 v dropout voltage (v do ) output current = 1 ma output current = 50 ma ? ? 10 500 tbd tbd mv output voltage (v dd ) output current = 1 to 50 ma reg0md = ?0? reg0md = ?1? tbd tbd 2.1 2.5 tbd tbd v bias current reg0md = ?0? reg0md = ?1? ? ? 1 1 tbd tbd a dropout indicator detection threshold ? 50 ? mv output voltage tempco ? 350 ? v/oc vreg settling time 50 ma load with v regin = 2.5 v and v dd load capacitor of 4.8 f ? 250 ? s *note: the minimum input voltage is 2.15 v or v dd + v do (max load), whichever is greater. bit 7: regdis: voltage regulator disable bit. this bit disables/enables the voltage regulator. 0: voltage regulator enabled. 1: voltage regulator disabled. bit 6: reserved. read = 0b. must write 0b. bit 5: unused. read = 0b. write = don?t care. bit 4: reg0md: voltage regulator mode select bit. this bit selects the voltage regulator output voltage. 0: voltage regulator output is 2.1 v. 1: voltage regulator output is 2.5 v (default). bits 3?1: unused. read = 0b. write = don?t care. bit 0: dropout: voltage regulator dropout indicator bit. 0: voltage regulator is not in dropout. 1: voltage regulator is in or near dropout. r/w r/w r r/w r r r r reset value regdis reserved ? reg0md ? ? ? dropout 00010000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc9
rev. 0.8 83 C8051F410/1/2/3 9. comparators c8051f41x devices include two on-chip programmable voltage comparators: comparator0 is shown in figure 9.1 ; comparator1 is shown in figure 9.2 . the two comparators operate identically, but only comparator0 can be used as a reset source. the comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the port pins: a synchronous ?latched? output (cp0, cp1), or an asynchronous ?raw? output (cp0a, cp1a). the asynchronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output with the device in stop or suspend mode. when assigned to a port pin, the comparator output may be configured as open drain or push-pull (see section ?18.2. port i/o initialization? on page 151 ). comparator0 may also be used as a reset source (see section ?15.5. comparator0 reset? on page 130 ). the comparator0 inputs are selected in the cpt0mx register (sfr definition 9.2). the cmx0p3-cmx0p0 bits select the comparator0 positive input; the cmx0n3-cmx0n0 bits select the comparator0 negative input. the comparator1 inputs are selected in the cpt1mx register ( sfr definition 9.4 ). the cmx1p3- cmx1p0 bits select the comparator1 positive input; the cmx1n3-cmx1n0 bits select the comparator1 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con - figured as analog inputs in their associated port configuration register (with a ?1? written to the correspond - ing port latch register), and configured to be skipped by the crossbar (for details on port configuration, see section ?18.3. general purpose port i/o? on page 154 ) figure 9.1. comparator0 functional block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - p 0.1 p 0.3 p 0.5 p 0.7 cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling-edge cp0 interrupt p 1.1 p 1.3 p 1.5 p 1.7 p 2.1 p 2.3 p 2.5 p 2.7 p0.0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 p2.0 p2.2 p2.4 p2.6
C8051F410/1/2/3 84 rev. 0.8 the comparator output can be polled in software, used as an interrupt source, internal oscillator suspend awakening source and/or routed to a port pin. when routed to a port pin, the comparator output is avail - able asynchronous or synchronous to the system clock; the asynchronous output is available even in stop or suspend mode (with no system clock active). when disabled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and its supply current falls to less than 100 na. see section ?18.1. priority crossbar decoder? on page 149 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from -0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator electrical specifications are given in ta b l e 9.1 . the comparator response time may be configured in software via the cptnmd registers (see sfr defini - tion 9.3 and sfr definition 9.5 ). selecting a longer response time reduces the comparator supply current. see table 9.1 for complete timing and current consumption specifications. figure 9.2. comparator1 functional block diagram vdd cpt1cn + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp1 + p0.0 p0.2 p0.4 p0.6 cp1 - p 0.1 p 0.3 p 0.5 p 0.7 cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt1mx cmx1n3 cmx1n2 cmx1n1 cmx1n0 cmx1p3 cmx1p2 cmx1p1 cmx1p0 cpt1md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 rising-edge cp1 falling-edge cp1 interrupt p1.0 p1.2 p1.4 p1.6 p2.0 p2.2 p2.4 p2.6 p 1.1 p 1.3 p 1.5 p 1.7 p 2.1 p 2.3 p 2.5 p 2.7
rev. 0.8 85 C8051F410/1/2/3 figure 9.3. comparator hysteresis plot the comparator hysteresis is software-programmable via its comparator control register cptncn (for n = 0 or 1). the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator hysteresis is programmed using bits3-0 in the comparator control register cptncn (shown in sfr definition 9.1 and sfr definition 9.6 ). the amount of negative hysteresis voltage is determined by the settings of the cpnhyn bits. as shown in ta b l e 9.1 , settings of 20, 10 or 5 mv of negative hysteresis can be programmed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by setting the cpnhyp bits. comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (for inter - rupt enable and priority control, see section ?12. interrupt handler? on page 110 ). the cpnfif flag is set to logic 1 upon a comparator falling-edge detect, and the cpnrif flag is set to logic 1 upon the com - parator rising-edge detect. once set, these bits remain set until cleared by software. the output state of the comparator can be obtained at any time by reading the cpnout bit. the comparator is enabled by setting the cpnen bit to logic 1, and is disabled by clearing this bit to logic 0. the output state of the comparator can be obtained at any time by reading the cpnout bit. the compar - ator is enabled by setting the cpnen bit to logic 1, and is disabled by clearing this bit to logic 0. when the comparator is enabled, the internal oscillator is awakened from suspend mode if the comparator output is logic 0. note that false rising edges and falling edges can be detected when the comparator is first powered-on or if changes are made to the hysteresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. this power up time is specified in ta b le 9.1 on page 92 . positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol
C8051F410/1/2/3 86 rev. 0.8 sfr definition 9.1. cpt0cn: comparator0 control bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0?. 1: voltage on cp0+ > cp0?. bit5: cp0rif: comparator0 rising-edge flag. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. bit4: cp0fif: comparator0 falling-edge flag. 0: no comparator0 falling-edge has occurred since this flag was last cleared. 1: comparator0 falling-edge has occurred. bits3?2: cp0hyp1?0: comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp0hyn1?0: comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9b
rev. 0.8 87 C8051F410/1/2/3 sfr definition 9.2. cpt0mx: comparator0 mux selection bits7?4: cmx0n3?cmx0n0: comparator0 negative input mux select. these bits select which port pin is used as the comparator0 negative input. *note: available only on the C8051F410/2. bits1?0: cmx0p3?cmx0p0: comparator0 positive input mux select. these bits select which port pin is used as the comparator0 positive input. *note: available only on the C8051F410/2. r/w r/w r/w r/w r/w r/w r/w r/w reset value cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f cmx0n3 cmx0n2 cmx0n1 cmx0n0 negative input 0000 p0.1 0001 p0.3 0010 p0.5 0011 p0.7 0100 p1.1 0101 p1.3 0110 p1.5 0111 p1.7 1000 p2.1 1001 p2.3 * 1010 p2.5 * 1011 p2.7 11xxreserved cmx0p3 cmx0p2 cmx0p1 cmx0p0 positive input 0000 p0.0 0001 p0.2 0010 p0.4 0011 p0.6 0100 p1.0 0101 p1.2 0110 p1.4 0111 p1.6 1000 p2.0 1001 p2.2 1010 p2.4 * 1011 p2.6 * 11xxreserved
C8051F410/1/2/3 88 rev. 0.8 sfr definition 9.3. cpt0md: comparator0 mode selection bit7: reserved. read = 0b. must write 0b. bit6: unused. read = 0b. write = don?t care. bit5: cp0rie: comparator rising-edge interrupt enable. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. bit4: cp0fie: comparator falling-edge interrupt enable. 0: comparator falling-edge interrupt disabled. 1: comparator falling-edge interrupt enabled. bits3?2: unused. read = 00b. write = don?t care. bits1?0: cp0md1?cp0md0: comparator0 mode select these bits select the response time for comparator0. note: rising edge response times are approximately double the falling edge response times. r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved - cp0rie cp0fie - - cp0md1 cp0md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d mode cp0md1 cp0md0 cp0 falling edge response time (typ) 0 0 0 fastest response time 101 ? 210 ? 3 1 1 lowest power consumption
rev. 0.8 89 C8051F410/1/2/3 sfr definition 9.4. cpt1mx: comparator1 mux selection bits7?4: cmx1n3?cmx1n0: comparator1 negative input mux select. these bits select which port pin is used as the comparator1 negative input. *note: available only on the C8051F410/2. bits3?0: cmx1p3?cmx1p0: comparator1 positive input mux select. these bits select which port pin is used as the comparator1 positive input. *note: available only on the C8051F410/2. r/w r/w r/w r/w r/w r/w r/w r/w reset value cmx1n3 cmx1n2 cmx1n1 cmx1n0 cmx1p3 cmx1p2 cmx1p1 cmx1p0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9e cmx1n3 cmx1n2 cmx1n1 cmx1n0 negative input 0000 p0.1 0001 p0.3 0010 p0.5 0011 p0.7 0100 p1.1 0101 p1.3 0110 p1.5 0111 p1.7 1000 p2.1 1001 p2.3 * 1010 p2.5 * 1011 p2.7 11xxreserved cmx1p3 cmx1p2 cmx1p1 cmx1p0 positive input 0000 p0.0 0001 p0.2 0010 p0.4 0011 p0.6 0100 p1.0 0101 p1.2 0110 p1.4 0111 p1.6 1000 p2.0 1001 p2.2 1010 p2.4 * 1011 p2.6 * 11xxreserved
C8051F410/1/2/3 90 rev. 0.8 sfr definition 9.5. cpt1md: comparator1 mode selection bit7: reserved. read = 0b. must write 0b. bit6: unused. read = 0b. write = don?t care. bit5: cp1rie: comparator rising-edge interrupt enable. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. bit4: cp1fie: comparator falling-edge interrupt enable. 0: comparator falling-edge interrupt disabled. 1: comparator falling-edge interrupt enabled. bits3?2: unused. read = 00b. write = don?t care. bits1?0: cp1md1?cp1md0: comparator1 mode select. these bits select the response time for comparator1. note: rising edge response times are approximately double the falling edge response times. r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved - cp1rie cp1fie - - cp1md1 cp1md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9c mode cp1md1 cp1md0 cp1 falling edge response time (typ) 0 0 0 fastest response time 101 ? 210 ? 3 1 1 lowest power consumption
rev. 0.8 91 C8051F410/1/2/3 sfr definition 9.6. cpt1cn: comparator1 control bit7: cp1en: comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. bit6: cp1out: comparator1 output state flag. 0: voltage on cp1+ < cp1-. 1: voltage on cp1+ > cp1-. bit5: cp1rif: comparator1 rising-edge flag. 0: no comparator1 rising edge has occurred since this flag was last cleared. 1: comparator1 rising edge has occurred. bit4: cp1fif: comparator1 falling-edge flag. 0: no comparator1 falling-edge has occurred since this flag was last cleared. 1: comparator1 falling-edge has occurred. bits3?2: cp1hyp1?0: comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp1hyn1?0: comparator1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9a
C8051F410/1/2/3 92 rev. 0.8 table 9.1. comparator electrical characteristics v dd = 2.0 v, ?40 to +85 c unless otherwise noted. all specifications apply to both comparator0 and comparator1 unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm 1 = 1.5 v cp0+ ? cp0? = 100 mv ? 120 ? ns cp0+ ? cp0? = ?100 mv ? 160 ? ns response time: mode 1, vcm 1 = 1.5 v cp0+ ? cp0? = 100 mv ? 200 ? ns cp0+ ? cp0? = ?100 mv ? 340 ? ns response time: mode 2, vcm 1 = 1.5 v cp0+ ? cp0? = 100 mv ? 360 ? ns cp0+ ? cp0? = ?100 mv ? 720 ? ns response time: mode 3, vcm 1 = 1.5 v cp0+ ? cp0? = 100 mv ? 2.2 ? s cp0+ ? cp0? = ?100 mv ? 7.2 ? s common-mode rejection ratio ? 1.5 tbd mv/v positive hysteresis 1 cp0hyp1-0 = 00 ? 0.5 2.0 mv positive hysteresis 2 cp0hyp1-0 = 01 tbd 4.5 tbd mv positive hysteresis 3 cp0hyp1-0 = 10 tbd 9.0 tbd mv positive hysteresis 4 cp0hyp1-0 = 11 tbd 18.0 tbd mv negative hysteresis 1 cp0hyn1-0 = 00 ? ?0.5 ?2.0 mv negative hysteresis 2 cp0hyn1-0 = 01 tbd ?4.5 tbd mv negative hysteresis 3 cp0hyn1-0 = 10 tbd ?9.0 tbd mv negative hysteresis 4 cp0hyn1-0 = 11 tbd ?18.0 tbd mv inverting or non-inverting input voltage range ?0.25 ? v dd + 0.25 v input capacitance ? 4 ? pf input bias current ? 0.5 ? na input offset voltage ?10 ? 10 mv power supply power supply rejection 2 ? 0.2 tbd mv/v power-up time ? 2.3 ? s supply current at dc mode 0 ? 13 tbd a mode 1 ? 6.0 tbd a mode 2 ? 3.0 tbd a mode 3 ? 1.0 tbd a notes: 1. vcm is the common-mode voltage on cp0+ and cp0?. 2. guaranteed by design and/or characterization.
rev. 0.8 93 C8051F410/1/2/3 10. cip-51 microcontroller the mcu system controller core is the cip-51 microcontroller. the cip-51 is fully compatible with the mcs-51? instruction set. standard 803x/805x assemblers and compilers can be used to develop soft - ware. the c8051f41x family has a superset of all the peripherals included with a standard 8051. see sec - tion ? 1. system overview ? on page 19 for more information about the available peripherals. the cip-51 includes on-chip debug hardware which interfaces directly with the analog and digital subsystems, provid - ing a complete data acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see figure 10.1 for a block diagram). the cip-51 core includes the following features: figure 10.1. cip-51 block diagram - fully compatible with mcs-51 instruction set - 50 mips peak throughput - 256 bytes of internal ram - extended interrupt handler - reset input - power management modes - integrated debug logic data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8
C8051F410/1/2/3 94 rev. 0.8 performance the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan - dard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's system clock running at 50 mhz, it has a peak throughput of 50 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon labs 2-wire (c2) interface. note that the re-programmable flash can also be read and written a single byte at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data storage as well as updat - ing program code under software control. the on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and mem - ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. the cip-51 is supported by development tools from silicon laboratories, inc. and third party vendors. sili - con laboratories provides an integrated development environment (ide) including editor, evaluation com - piler, assembler, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the on-chip debug logic to provide fast and efficient in-system device programming and debugging. third party macro assemblers and c compilers are also available. 10.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and functional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, instruction timing is different than that of the stan - dard 8051. 10.1.1. instruction and cpu timing in many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instructions take two less clock cycles to complete when the branch is not taken as opposed to when the branch is taken. ta b le 10.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 2 2/4 3 3/5 4 5 4/6 6 8 number of instructions 26 50 5 10 7 5 2 1 2 1
rev. 0.8 95 C8051F410/1/2/3 10.1.2. movx instruction and program memory the movx instruction is typically used to access data stored in xdata memory space. in the cip-51, the movx instruction can also be used to write or erase on-chip program memory space implemented as re- programmable flash memory. the flash access feature provides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile data storage. refer to section ?16. flash memory? on page 135 for further details. table 10.1. cip-51 instruction set summary 1 mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2
C8051F410/1/2/3 96 rev. 0.8 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 4 to 7 2 movc a, @a+pc move code byte relative pc to a 1 4 to 7 2 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 table 10.1. cip-51 instruction set summary 1 (continued) mnemonic description bytes clock cycles
rev. 0.8 97 C8051F410/1/2/3 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/4 jnc rel jump if carry is not set 2 2/4 jb bit, rel jump if direct bit is set 3 3/5 jnb bit, rel jump if direct bit is not set 3 3/5 jbc bit, rel jump if direct bit is set and clear bit 3 3/5 program branching acall addr11 absolute subroutine call 2 4 lcall addr16 long subroutine call 3 5 ret return from subroutine 1 6 reti return from interrupt 1 6 ajmp addr11 absolute jump 2 4 ljmp addr16 long jump 3 5 sjmp rel short jump (relative address) 2 4 jmp @a+dptr jump indirect relative to dptr 1 4 jz rel jump if a equals zero 2 2/4 jnz rel jump if a does not equal zero 2 2/4 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/5 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/5 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/6 djnz rn, rel decrement register and jump if not zero 2 2/4 djnz direct, rel decrement direct byte and jump if not zero 3 3/5 nop no operation 1 1 notes: 1. assumes pfen = 1 for all instruction timing. 2. movc instructions take 4 to 7 clock cycles depending on instruction alignment and the flrt setting ( sfr definition 16.3. flscl: flash scale ). table 10.1. cip-51 instruction set summary 1 (continued) mnemonic description bytes clock cycles
C8051F410/1/2/3 98 rev. 0.8 10.2. register descriptions following are descriptions of sfrs related to the operation of the cip-51 system controller. reserved bits should not be set to logic 1. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. detailed descrip - tions of the remaining sfrs are included in the sections of the datasheet associated with their correspond - ing system function. sfr definition 10.1. sp: stack pointer notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00- 0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination must be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall and ljmp. the destination may be anywhere within the 8k-byte program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. bits7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp register defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81
rev. 0.8 99 C8051F410/1/2/3 sfr definition 10.2. dpl: data pointer low byte sfr definition 10.3. dph: data pointer high byte bits7?0: dpl: data pointer low. the dpl register is the low byte of the 16-bit dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 bits7?0: dph: data pointer high. the dph register is the high byte of the 16-bit dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83
C8051F410/1/2/3 100 rev. 0.8 sfr definition 10.4. psw: program status word bit7: cy: carry flag. this bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). it is cleared to 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to 0 by all other arithmetic operations. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4?3: rs1?rs0: register bank select. these bits select which register bank is used during register accesses. bit2: ov: overflow flag. this bit is set to 1 under the following circumstances: an add, addc, or subb instruction causes a sign-change overflow. a mul instruction results in an overflow (result is greater than 255). a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div instructions in all other cases. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. this bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. r/w r/w r/w r/w r/w r/w r/w r reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xd0 rs1 rs0 register bank address 0 0 0 0x00?0x07 0 1 1 0x08?0x0f 1 0 2 0x10?0x17 1 1 3 0x18?0x1f
rev. 0.8 101 C8051F410/1/2/3 sfr definition 10.5. acc: accumulator sfr definition 10.6. b: b register 10.3. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and internal clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode consumes the least power. sfr defini - tion 10.7 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off the oscil - lators lowers power consumption considerably; however a reset is required to restart the mcu. the c8051f41x devices feature a low-power suspend mode, which stops the internal oscillator until a wakening event occurs. see section ? 19.1.1. internal oscillator suspend mode ? on page 166 . bits7?0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xe0 bits7?0: b: b register. this register serves as a second accumulator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xf0
C8051F410/1/2/3 102 rev. 0.8 10.3.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (reti) will be the instruction immediately following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. this pro - vides the opportunity for additional power savings, allowing the system to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. 10.3.2. stop mode setting the stop mode select bit (pcon.1) causes the cip-51 to enter stop mode as soon as the instruc - tion that sets the bit completes execution. in stop mode the internal oscillator, cpu, and all digital peripher - als are stopped; the state of the external oscillator circuit is not affected. each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an internal reset and thereby terminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout period of 100 s. 10.3.3. suspend mode the c8051f41x devices feature a low-power suspend mode, which stops the internal oscillator until a wakening event occurs. see section ?19.1.1. internal oscillator suspend mode? on page 166 . sfr definition 10.7. pcon: power control bits7?2: reserved. bit1: stop: stop mode select. writing a ?1? to this bit will place the cip-51 into stop mode. this bit will always read ?0?. 1: cip-51 forced into power-down mode. (turns off internal oscillator). bit0: idle: idle mode select. writing a ?1? to this bit will place the cip-51 into idle mode. this bit will always read ?0?. 1: cip-51 forced into idle mode. (shuts off clock to cpu, but clock to timers, interrupts, and all peripherals remain active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved reserved reserved reserved reserved stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87
rev. 0.8 103 C8051F410/1/2/3 11. memory organization and sfrs the memory organization of the c8051f41x is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory map is shown in figure 11.1 . figure 11.1. memory map 11.1. program memory the cip-51 core has a 64k-byte program memory space. the C8051F410/1 implement 32 kb of this pro - gram memory space as in-system, re-programmable flash memory, organized in a contiguous block from addresses 0x0000 to 0x7dff. addresses above 0x7dff are reserved on the 32 kb devices. the c8051f412/3 implement 16 kb of flash from addresses 0x0000 to 0x3fff. program memory is normally assumed to be read-only. however, the c8051f41x can write to program memory by setting the program store write enable bit (psctl.0) and using the movx write instruction. this feature provides a mechanism for updates to program code and use of the program memory space for non-volatile data storage. refer to section ?16. flash memory? on page 135 for further details. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 2048 bytes (accessible using movx instruction) 0x0000 0x07ff same 2048 bytes as from 0x0000 to 0x07ff, wrapped on 2048-byte boundaries 0x0800 0xffff 32 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x7e00 0x7dff ?f410/1 16 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x4000 0x3fff ?f412/3
C8051F410/1/2/3 104 rev. 0.8 11.2. data memory the c8051f41x includes 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of general purpose registers, each bank con - sisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function registers (sfrs) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instruct ions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 11.1 illustrates the data memory organization of the c8051f41x. the c8051f41x family also includes 2048 bytes of on-chip ram mapped into the external memory (xdata) space. this ram can be accessed using the cip-51 core?s movx instruction. more information on the xram memory can be found in section ?17. external ram? on page 145 . 11.3. general purpose registers the lower 32 bytes of data memory (locations 0x00 through 0x1f) may be addressed as four banks of general-purpose registers. each bank consists of eight byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bits in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 10.4. psw: program status word ). this allows fast context switching when entering subroutines and interrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 11.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 11.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp, 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp+1 and then sp is incremented. a reset initializes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes.
rev. 0.8 105 C8051F410/1/2/3 11.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the special function registers (sfrs). the sfrs provide control and data exchange with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to configure and access the sub-systems unique to the mcu. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruction set. ta b le 11.1 lists the sfrs implemented in the cip-51 system controller. the sfr registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, tcon, ie, etc.) are bit-addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing these areas will have an indeterminate effect and should be avoided. refer to the corresponding pages of the data sheet, as indicated in ta b l e 11.2 , for a detailed description of each register. table 11.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 b p0mdin p1mdin p2mdin ida1l ida1h eip1 eip2 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 acc xbr0 xbr1 pfe0cn it01cf eie1 eie2 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 crc0flip d0 psw ref0cn pca0cpl5 pca0cph5 p0skip p1skip p2skip p0mat c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h pca0cpm5 p1mat c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth p0mask b8 ip ida0cn adc0tk adc0mx adc0cf adc0l adc0h p1mask b0 p0oden oscxcn oscicn oscicl ida1cn flscl flkey a8 ie clksel emi0cn clkmul rtc0adr rtc0dat rtc0key oneshot a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout 98 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h ida0l ida0h 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph crc0cn crc0in crc0dat pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
C8051F410/1/2/3 106 rev. 0.8 table 11.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 101 adc0cf 0xbc adc0 configuration 60 adc0cn 0xe8 adc0 control 62 adc0h 0xbe adc0 61 adc0l 0xbd adc0 61 adc0gth 0xc4 adc0 greater-than data high byte 64 adc0gtl 0xc3 adc0 greater-than data low byte 64 adc0lth 0xc6 adc0 less-than data high byte 65 adc0ltl 0xc5 adc0 less-than data low byte 65 adc0mx 0xc6 adc0 channel select 59 adc0tk 0xba adc0 tracking mode select 63 b0xf0 b register 101 ckcon 0x8e clock control 237 clkmul 0xab clock multiplier 173 clksel 0xa9 clock select 174 cpt0cn 0x9b comparator0 control 86 cpt0md 0x9d comparator0 mode selection 88 cpt0mx 0x9f comparator0 mux selection 87 cpt1cn 0x9a comparator1 control 91 cpt1md 0x9c comparator1 mode selection 90 cpt1mx 0x9e comparator1 mux selection 89 crc0cn 0x84 crc0 control 124 crc0in 0x85 crc0 data input 124 crc0dat 0x86 crc0 data output 125 crc0flip 0xdf crc0 bit flip 125 dph 0x83 data pointer high 99 dpl 0x82 data pointer low 99 eie1 0xe6 extended interrupt enable 1 114 eie2 0xe7 extended interrupt enable 2 116 eip1 0xf6 extended interrupt priority 1 115 eip2 0xf7 extended interrupt priority 2 116 emi0cn 0xaa external memory interface control 145 flkey 0xb7 flash lock and key 141 flscl 0xb6 flash scale 142 ida0h 0x97 current mode dac0 high byte 71 ida0l 0x96 current mode dac0 low byte 72 ida0cn 0xb9 current mode dac0 control 71 ida1h 0xf5 current mode dac1 high byte 73
rev. 0.8 107 C8051F410/1/2/3 ida1l 0xf4 current mode dac1 low byte 73 ida1cn 0xb5 current mode dac1 control 72 ie 0xa8 interrupt enable 112 ip 0xb8 interrupt priority 113 it01cf 0xe4 int0/int1 configuration 118 oneshot 0xaf flash oneshot period 143 oscicl 0xb3 internal oscillator calibration 167 oscicn 0xb2 internal oscillator control 167 oscxcn 0xb1 external oscillator control 171 p0 0x80 port 0 latch 155 p0mask 0xc7 port 0 mask 157 p0mat 0xd7 port 0 match 157 p0mdin 0xf1 port 0 input mode configuration 155 p0mdout 0xa4 port 0 output mode configuration 156 p0oden 0xb0 port 0 overdrive 157 p0skip 0xd4 port 0 skip 156 p1 0x90 port 1 latch 158 p1mask 0xbf port 1 mask 160 p1mat 0xcf port 1 match 160 p1mdin 0xf2 port 1 input mode configuration 158 p1mdout 0xa5 port 1 output mode configuration 159 p1skip 0xd5 port 1 skip 159 p2 0xa0 port 2 latch 161 p2mdin 0xf3 port 2 input mode configuration 161 p2mdout 0xa6 port 2 output mode configuration 162 p2skip 0xd6 port 2 skip 162 pca0cn 0xd8 pca control 261 pca0cph0 0xfc pca capture 0 high 264 pca0cph1 0xea pca capture 1 high 264 pca0cph2 0xec pca capture 2 high 264 pca0cph3 0xee pca capture 3 high 264 pca0cph4 0xfe pca capture 4 high 264 pca0cph5 0xd3 pca capture 5 high 264 pca0cpl0 0xfb pca capture 0 low 264 pca0cpl1 0xe9 pca capture 1 low 264 pca0cpl2 0xeb pca capture 2 low 264 pca0cpl3 0xed pca capture 3 low 264 pca0cpl4 0xfd pca capture 4 low 264 table 11.2. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
C8051F410/1/2/3 108 rev. 0.8 pca0cpl5 0xd2 pca capture 5 low 264 pca0cpm0 0xda pca module 0 mode 263 pca0cpm1 0xdb pca module 1 mode 263 pca0cpm2 0xdc pca module 2 mode 263 pca0cpm3 0xdd pca module 3 mode 263 pca0cpm4 0xde pca module 4 mode 263 pca0cpm5 0xce pca module 5 mode 263 pca0h 0xfa pca counter high 264 pca0l 0xf9 pca counter low 264 pca0md 0xd9 pca mode 262 pcon 0x87 power control 102 pfe0cn 0xe3 prefetch engine control 119 psctl 0x8f program store r/w control 141 psw 0xd0 program status word 100 ref0cn 0xd1 voltage reference control 78 reg0cn 0xc9 voltage regulator control 82 rtc0adr 0xac smartclock address 181 rtc0dat 0xad smartclock data 182 rtc0key 0xae smartclock lock and key 180 rstsrc 0xef reset source configuration/status 133 sbuf0 0x99 uart0 data buffer 213 scon0 0x98 uart0 control 212 smb0cf 0xc1 smbus configuration 197 smb0cn 0xc0 smbus control 199 smb0dat 0xc2 smbus data 201 sp 0x81 stack pointer 98 spi0cfg 0xa1 spi configuration 223 spi0ckr 0xa2 spi clock rate control 225 spi0cn 0xf8 spi control 224 spi0dat 0xa3 spi data 226 tcon 0x88 timer/counter control 235 th0 0x8c timer/counter 0 high 238 th1 0x8d timer/counter 1 high 238 tl0 0x8a timer/counter 0 low 238 tl1 0x8b timer/counter 1 low 238 tmod 0x89 timer/counter mode 236 tmr2cn 0xc8 timer/counter 2 control 242 tmr2h 0xcd timer/counter 2 high 243 table 11.2. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
rev. 0.8 109 C8051F410/1/2/3 tmr2l 0xcc timer/counter 2 low 243 tmr2rlh 0xcb timer/counter 2 reload high 243 tmr2rll 0xca timer/counter 2 reload low 243 tmr3cn 0x91 timer/counter 3control 247 tmr3h 0x95 timer/counter 3 high 248 tmr3l 0x94 timer/counter 3 low 248 tmr3rlh 0x93 timer/counter 3 reload high 248 tmr3rll 0x92 timer/counter 3 reload low 248 vdm0cn 0xff v dd monitor control 130 xbr0 0xe1 port i/o crossbar control 0 153 xbr1 0xe2 port i/o crossbar control 1 154 table 11.2. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
C8051F410/1/2/3 110 rev. 0.8 12. interrupt handler the c8051f41x family includes an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. the allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. each interrupt source has one or more associ - ated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid inter - rupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. as soon as execution of the current instruction is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the interrupt enable and extended interrupt enable sfrs. however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recog - nized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt- enable settings. note that interrupts which occur when the ea bit is set to logic 0 will be held in a pending state, and will not be serviced until the ea bit is set back to logic 1. some interrupt-pending flags are automatically cleared by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interrupt request will be generated immediately and the cpu will re-enter the isr after the completion of the next instruction. 12.1. mcu interrupt so urces and vectors the mcus support 18 interrupt sources. software can simulate an interrupt by setting any interrupt-pend - ing flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated and the cpu will vector to the isr address associated with the interrupt-pending flag. mcu interrupt sources, associ - ated vector addresses, priority order, and control bits are summarized in table 12.1 on page 111 . refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid inter - rupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 12.2. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be preempted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 12.1 . 12.3. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each system clock cycle. therefore, the fastest possible response time is 7 system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and 5 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is executed, a sin - gle instruction is executed before an lcall is made to service the pending interrupt. therefore, the maxi - mum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performi ng an reti instruction followed by a div as the next
rev. 0.8 111 C8051F410/1/2/3 instruction. in this case, the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 5 clock cycles to exe - cute the lcall to the isr. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current is r completes, including the reti and following instruc - tion. table 12.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highest external interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) smartclock 0x0043 8 alrm (rtc0cn.2) oscfail (rtc0cn.5) n n ertc0 (eie1.1) prtc0 (eip1.1) adc0 window comparator 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2) adc0 end of conversion 0x0053 10 ad0int (adc0sta.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie1.6) pcp1 (eip1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) pt3 (eip1.7) voltage regulator dropout 0x007b 15 n/a n/a n/a ereg0 (eie2.0) preg0 (eip2.0) port match 0x0083 16 n/a n/a n/a emat (eie2.1) pmat (eip2.1)
C8051F410/1/2/3 112 rev. 0.8 12.4. interrupt regi ster descriptions the sfrs used to enable the interrupt sources and set their priority level are described below. refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). sfr definition 12.1. ie: interrupt enable bit 7: ea: global interrupt enable. this bit globally enables/disables all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. bit 6: espi0: enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. bit 5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. bit 4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. bit 3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit 2: ex1: enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit 1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit 0: ex0: enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea espi0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xa8
rev. 0.8 113 C8051F410/1/2/3 sfr definition 12.2. ip: interrupt priority bit 7: unused. read = 1, write = don't care. bit 6: pspi0: serial peripheral interface (spi0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. bit 5: pt2: timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. bit 4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. bit 3: pt1: timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. bit 2: px1: external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit 1: pt0: timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. bit 0: px0: external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. r r/w r/w r/w r/w r/w r/w r/w reset value - pspi0 pt2 ps0 pt1 px1 pt0 px0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xb8
C8051F410/1/2/3 114 rev. 0.8 sfr definition 12.3. eie1: extended interrupt enable 1 bit 7: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. bit 6: ecp1: enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. bit 5: ecp0: enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. bit 4: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pca0 interrupts. 1: enable interrupt requests generated by pca0. bit 3: eadc0: enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. bit 2: ewadc0: enable adc0 window comparison interrupt. this bit sets the masking of the adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by the ad0wint flag. bit 1: ertc0: enable smartclock interrupt. this bit sets the masking of the smartclock interrupt. 0: disable smartclock interrupts. 1: enable interrupt requests generated by the alrm and oscfail flag. bit 0: esmb0: enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. r/w r/w r/w r/w r/w r/w r/w r/w reset value et3 ecp1 ecp0 epca0 eadc0 ewadc0 ertc0 esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6
rev. 0.8 115 C8051F410/1/2/3 sfr definition 12.4. eip1: extended interrupt priority 1 bit 7: pt3: timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. bit 6: pcp1: comparator1 (cp1) interrupt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. bit 5: pcp0: comparator0 (cp0) interrupt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. bit 4: ppca0: programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit 3: padc0: adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete interrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. bit 2: pwadc0: adc0 window comparison interrupt priority control. this bit sets the priority of the adc0 window comparison interrupt. 0: adc0 window comparison interrupt set to low priority level. 1: adc0 window comparison interrupt set to high priority level. bit 1: prtc0: smartclock interrupt priority control. this bit sets the priority of the smartclock interrupt. 0: smartclock interrupt set to low priority level. 1: smartclock interrupt set to high priority level. bit 0: psmb0: smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value pt3 pcp1 pcp0 ppca0 padc0 pwadc0 prtc0 psmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6
C8051F410/1/2/3 116 rev. 0.8 sfr definition 12.5. eie2: extended interrupt enable 2 sfr definition 12.6. eip2: extended interrupt priority 2 bits 7?2: unused. read = 000000b. write = don?t care. bit 1: emat: enable port match interrupt. this bit sets the masking of the port match interrupt. 0: disable the port match interrupt. 1: enable the port match interrupt. bit 0: ereg0: enable voltage regulator interrupt. this bit sets the masking of the voltage regulator dropout interrupt. 0: disable the voltage regulator dropout interrupt. 1: enable the voltage regulator dropout interrupt. r/w r/w r/w r/w r/w r/w r/w r/w reset value ------ematereg000000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe7 bits 7?2: unused. read = 000000b. write = don?t care. bit 1: emat: port match interrupt priority control. this bit sets the priority of the port match interrupt. 0: port match interrupt set to low priority level. 1: port match interrupt set to high priority level. bit 0: preg0: voltage regulator interrupt priority control. this bit sets the priority of the voltage regulator interrupt. 0: voltage regulator interrupt set to low priority level. 1: voltage regulator interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value ------pmatpreg000000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf7
rev. 0.8 117 C8051F410/1/2/3 12.5. external interrupts the /int0 and /int1 external interrupt sources are configurable as active high or low, edge or level sensi - tive. the in0pl (/int0 polarity) and in1pl (/int1 polarity ) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?24.1. timer 0 and timer 1? on page 231 ) select level or edge sensitive. the table below lists the possible configurations. /int0 and /int1 are assigned to port pins as defined in the it01cf register (see sfr definition 12.7). note that /int0 and /int0 port pin assignments are independent of any crossbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int0 and/or /int1, configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?18.1. priority crossbar decoder? on page 149 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corre - sponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); the flag remains logic 0 while the input is inac - tive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request before execution of the isr completes or another interrupt request will be generated. it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 10 active low, edge sensitive 10 active low, edge sensitive 11 active high, edge sensitive 11 active high, edge sensitive 00 active low, level sensitive 00 active low, level sensitive 01 active high, level sensitive 01 active high, level sensitive
C8051F410/1/2/3 118 rev. 0.8 sfr definition 12.7. it01cf: int0/int1 configuration bit 7: in1pl: /int1 polarity 0: /int1 input is active low. 1: /int1 input is active high. bits 6?4: in1sl2?0: /int1 port pin selection bits these bits select which port pin is assigned to /int1. note that this pin assignment is inde- pendent of the crossbar; /int1 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). bit 3: in0pl: /int0 polarity 0: /int0 interrupt is active low. 1: /int0 interrupt is active high. bits 2?0: int0sl2?0: /int0 port pin selection bits these bits select which port pin is assigned to /int0. note that this pin assignment is inde- pendent of the crossbar. /int0 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). r/w r/w r/w r/w r/w r/w r/w r/w reset value in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 note: refer to sfr definition 24.1. ?tcon: timer control? on page 235 for int0/1 edge- or level-sensitive interrupt selection. in1sl2?0 /int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2?0 /int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7
rev. 0.8 119 C8051F410/1/2/3 13. prefetch engine the c8051f41x family of devices incorporate a 2-byte prefetch engine. due to flash access time specifi - cations, the prefetch engine is necessary for full-speed (50 mhz) code execution. instructions are read from flash memory two bytes at a time by the prefetch engine, and given to the cip-51 processor core to execute. when running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. when a code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from flash memory. the flrt bit (flscl.4) determines how many clock cycles are used to read each set of two code bytes from flash. when operating from a system clock of 25 mhz or less, the flrt bit should be set to ?0? so that the prefetch engine takes only one clock cycle for each read. when operating with a system clock of greater than 25 mhz (up to 50 mhz), the flrt bit should be set to ?1?, so that each prefetch code read lasts for two clock cycles. sfr definition 13.1. pfe0cn: prefetch engine control bits 7?6: unused. read = 00b; write = don?t care bit 5: pfen: prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. bits 4?1: unused. read = 0000b; write = don?t care bit 0: flbwe: flash block write enable. this bit allows block writes to flash memory from software. 0: each byte of a software flash write is written individually. 1: flash bytes are written in groups of two. note: the prefetch engine should be disabled when changes to flrt are made. see section ?16. flash memory? on page 135 . rrr/wrrrrr/wreset value pfen flbwe 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
C8051F410/1/2/3 120 rev. 0.8 n otes :
rev. 0.8 121 C8051F410/1/2/3 14. cyclic redundancy check unit (crc0) c8051f41x devices include a cyclic redundancy check unit (crc0) that can perform a crc using a 16-bit or 32-bit polynomial. crc0 accepts a stream of 8-bit data written to the crc0in register. crc0 posts the 16-bit or 32-bit result to an internal register. the internal result register may be accessed indirectly using the crc0pnt bits and crc0dat register, as shown in figure 14.1 . crc0 also has a bit reverse register for quick data manipulation. figure 14.1. crc0 block diagram 14.1. crc algorithm the c8051f41x crc unit generates a crc result equivalent to the following algorithm: step 1. xor the input with the most-significant bytes of the current crc result. if this is the first iteration of the crc unit, the current crc result will be the set initial value (0x00000000 or 0xffffffff). step 2a. if the msb of the crc result is set, shift the crc result and xor the result with the selected polynomial. step 2b. if the msb of the crc result is not set, shift the crc result. step 3. repeat steps 2a/2b for the number of input bits (8). crc0in 8 crc0dat crc0cn crc0sel crc0init crc0val crc0pnt1 crc0pnt0 crc engine 4 to 1 mux result 32 8 8 8 8 8
C8051F410/1/2/3 122 rev. 0.8 for example, the 16-bit 'f41x crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } // return the final remainder (crc value) return crc_acc; } the following table lists several input values and the associated outputs using the 16-bit 'f41x crc algo - rithm: table 14.1. example 16-bit crc outputs input output 0x63 0xbd35 0x8c 0xb1f4 0x7d 0x4eca 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166
rev. 0.8 123 C8051F410/1/2/3 14.2. preparing for a crc calculation to prepare crc0 for a crc calculation, software should select the desired polynomial and set the initial value of the result. two polynomials are available: 0x1021 (16-bit) and 0x04c11db7 (32-bit). the crc0 result may be initialized to one of two values: 0x00000000 or 0xffffffff. the following steps can be used to initialize crc0. step 1. select a polynomial (set crc0sel to ?0? for 32-bit or ?1? for 16-bit). step 2. select the initial result value (set crc0val to ?0? for 0x00000000 or ?1? for 0xffffffff). step 3. set the result to its initial value (write ?1? to crc0init). 14.3. performing a crc calculation once crc0 is initialized, the input data stream is sequentially written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. 14.4. accessing the crc0 result the internal crc0 result is 32-bits (crc0sel = 0b) or 16-bits (crc0sel = 1b). the crc0pnt bits select the byte that is targeted by read and write operations on crc0dat and increment after each read or write. the calculation result will remain in the internal cr0 result register until it is set, overwritten, or addi - tional data is written to crc0in. 14.5. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of each bit in a byte as shown in figure 14.2. each byte of data written to crc0flip is read back bit reversed. for example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathematical function used in algorithms such as the fft. figure 14.2. bit reverse register crc0flip write crc0flip read
C8051F410/1/2/3 124 rev. 0.8 sfr definition 14.1. crc0cn: crc0 control sfr definition 14.2. crc0in: crc0 data input bits 7?5: unused. read = 0b. write = don?t care. bit 4: crc0sel: crc0 polynomial select bit. 0: crc0 uses the 32-bit polynomial 0x04c11db7 for calculating the crc result. 1: crc0 uses the 16-bit polynomial 0x1021 for calculating the crc result. bit 3: crc0init: crc0 result initialization bit. writing a ?1? to this bit initializes the entire crc result based on crc0val. bit 2: crc0val: crc0 set value select bit this bit selects the set value of the crc result. 0: crc result is set to 0x00000000 on write of ?1? to crc0init. 1: crc result is set to 0xffffffff on write of ?1? to crc0init. bits 1?0: crc0pnt. crc0 result pointer. these bits specify which byte of the crc result will be read/written on the next access to crc0dat. the value of these bits will auto-increment upon each read or write. for crc0sel = 0: 00: crc0dat accesses bits 7?0 of the 16-bit crc result. 01: crc0dat accesses bits 15?8 of the 16-bit crc result. 10: crc0dat accesses bits 7?0 of the 16-bit crc result. 11: crc0dat accesses bits 15?8 of the 16-bit crc result. for crc0sel = 1: 00: crc0dat accesses bits 7?0 of the 32-bit crc result. 01: crc0dat accesses bits 15?8 of the 32-bit crc result. 10: crc0dat accesses bits 23?16 of the 32-bit crc result. 11: crc0dat accesses bits 31?24 of the 32-bit crc result. r r r r/w w r/w r/w r/w reset value - - - crc0sel crc0init crc0val crc0pnt 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x84 bits 7?0: crc0in: crc data input each write to crcin results in the written data being computed into the existing crc result. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x85
rev. 0.8 125 C8051F410/1/2/3 sfr definition 14.3. crc0dat: crc0 data output sfr definition 14.4. crc0flip: crc0 bit flip bits 7?0: crc0dat: indirect crc result data bits. each operation performed on crc0dat targets the crc result bits pointed to by crc0pnt. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x86 bits 7?0: crc0flip: crc bit flip. any byte written to crc0flip is read back in a bit-reversed order, i.e. the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the data read back will be 0x03. if 0x05 is written to crc0flip, the data read back will be 0xa0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xdf
C8051F410/1/2/3 126 rev. 0.8 n otes :
rev. 0.8 127 C8051F410/1/2/3 15. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, the following occur: cip-51 halts program execution special function registers (sfrs) are initialized to their defined reset values external port pins are forced to a known state interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any previously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lost, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter - nal oscillator. refer to section ?19. oscillators? on page 165 for information on selecting and configuring the system clock source. the watchdog timer is enabled with the system clock divided by 12 as its clock source ( section ?25.3. watchdog timer mode? on page 257 details the use of the watchdog timer). program execution begins at location 0x0000. figure 15.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel p x.x p x.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable illegal flash operation /rs t (wired-or) power on reset '0' + - comparator 0 vdd + - supply monitor enable smartclock rtc0re c0rsef
C8051F410/1/2/3 128 rev. 0.8 15.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . an additional delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 15.2 plots the power-on and v dd monitor reset timing. for valid ramp times (less than 1 ms), the power-on reset delay (t pordelay ) is typically less than 0.3 ms. note: the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. on exit from a power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc register are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000), software can read the porsf flag to determine if a power-up was the cause of reset. the contents of internal data memory should be assumed to be undefined after a power-on reset. the v dd monitor is disabled following a power-on reset. figure 15.2. power-on and v dd monitor reset timing power-on reset vdd monitor reset /rst t volt s 1.0 l ogic high logic low t pordelay v d d v rst vdd
rev. 0.8 129 C8051F410/1/2/3 15.2. power-fail reset / v dd monitor when the vdd monitor is selected as a reset source and a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 15.2 ). when v dd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is enabled and is selected as a reset source after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by software, and a software reset is performed, the v dd monitor will still be disabled after the reset. to protect the integrity of flash contents, the v dd monitor must be enabled to the higher setting (vdmlvl = '1') and selected as a reset source if soft - ware contains routines which erase or write flash memory. if the v dd monitor is not enabled, any erase or write performed on flash memory will cause a flash error device reset. the v dd monitor must be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabilized may cause a system reset. the procedure for re- enabling the v dd monitor and configuring the v dd monitor as a reset source is shown below: step 1. enable the v dd monitor (vdmen bit in vdm0cn = ?1?). step 2. wait for the v dd monitor to stabilize (approximately 5 s). note: this delay should be omitted if software contains routines which erase or write flash memory. step 3. select the v dd monitor as a reset source (porsf bit in rstsrc = ?1?). see figure 15.2 for v dd monitor timing; note that the reset delay is not incurred after a v dd monitor reset. see table 15.1 for complete electrical characteristics of the v dd monitor. note: software should take care not to inadvertently disable the v dd monitor as a reset source when writing to rstsrc to enable other reset sources or to trigger a software reset. all writes to rstsrc should explicitly set porsf to '1' to keep the v dd monitor enabled as a reset source.
C8051F410/1/2/3 130 rev. 0.8 sfr definition 15.1. vdm0cn: v dd monitor control 15.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see table 15.1 for complete rst pin specifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 15.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the system clock. if the system clock remains high or low for more than 100 s, the one-shot will time out and generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset. 15.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted reset. the comparator0 reset is active-low: if the non- bit7: vdmen: v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate system resets until it is also selected as a reset source in register rstsrc (sfr definition 15.2). the v dd monitor can be allowed to stabilize before it is selected as a reset source. selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. see table 15.1 for the minimum v dd monitor turn-on time. 0: v dd monitor disabled. 1: v dd monitor enabled (default). bit6: vddstat: v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. bit5: vdmlvl: v dd level select. 0: v dd monitor threshold is set to v rst-low (default). 1: v dd monitor threshold is set to v rst-high . this setting is recommended for any system that includes code that writes to and/or erases flash. bits4?0: reserved. read = variable. write = don?t care. r/w r r/w r r r r r reset value vdmen vddstat vdmlvl reserved reserved reserved reserved reserved 1v000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xff
rev. 0.8 131 C8051F410/1/2/3 inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. 15.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of control during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?25.3. watchdog timer mode? on page 257 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a reset is generated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset. 15.7. flash error reset if a flash read/write/erase or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation targets an address above the lock byte address. a flash read is attempted above user code space. this occurs when a movc operation targets an address above the lock byte address. a program read is attempted above user code space. this occurs when user code attempts to branch to an address above the lock byte address. a flash read, write or erase attempt is restricted due to a flash security setting (see section ?16.3. security options? on page 137 ). a flash write or erase is attempted while the v dd monitor is disabled. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset.
C8051F410/1/2/3 132 rev. 0.8 15.8. smartclock (real time clock) reset the smartclock can generate a system reset on two events: smartclock oscillator fail or smartclock alarm. the smartclock oscillator fail event occurs when the smartclock missing clock detector is enabled and the smartclock clock is below approximately 20 khz. a smartclock alarm event occurs when the smartclock alarm is enabled and the smartclock timer value matches the alarmn registers. the smartclock can be configured as a reset source by writing a ?1? to the rtc0re flag (rstsrc.7). the state of the rst pin is unaffected by this reset. 15.9. software reset software may force a reset by writing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset.
rev. 0.8 133 C8051F410/1/2/3 sfr definition 15.2. rstsrc: reset source note: for bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instructions read and modify the source enable only. [this applies to bits: rtc0re, c0rsef, swrsf, mcdrsf, porsf]. bit7: rtc0re: smartclock (real time clock) reset enable and flag. 0: read: source of last reset was not a smartclock alarm or oscillator fail event. write: smartclock is not a reset source. 1: read: source of last reset was a smartclock alarm or oscillator fail event. write: smartclock is a reset source. bit6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: c0rsef: comparator0 reset enable and flag. 0: read: source of last reset was not comparator0. write: comparator0 is not a reset source. 1: read: source of last reset was comparator0. write: comparator0 is a reset source (active-low). bit4: swrsf: software reset force and flag. 0: read: source of last reset was not a write to the swrsf bit. write: no effect. 1: read: source of last was a write to the swrsf bit. write: forces a system reset. bit3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit2: mcdrsf: missing clock detector flag. 0: read: source of last reset was not a missing clock detector timeout. write: missing clock detector disabled. 1: read: source of last reset was a missing clock detector timeout. write: missing clock detector enabled; triggers a reset if a missing clock condition is detected. bit1: porsf: power-on reset force and flag. this bit is set anytime a power-on reset occurs. writing this bit enables/disables the v dd monitor as a reset source. note: writing ?1? to this bit before the v dd monitor is enabled and stabilized may cause a system reset. see register vdm0cn (sfr definition 15.1) 0: read: last reset was not a power-on or v dd monitor reset. write: v dd monitor is not a reset source. 1: read: last reset was a power-on or v dd monitor reset; all other reset flags indeterminate. write: v dd monitor is a reset source. bit0: pinrsf: hw pin reset flag. 0: source of last reset was not rst pin. 1: source of last reset was rst pin. r/w r r/w r/w r r/w r/w r reset value rtc0re ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef
C8051F410/1/2/3 134 rev. 0.8 table 15.1. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.0 v ??tbd v rst input high voltage 0.7 x v dd ?? v rst input low voltage ? ? 0.3 x v dd v rst input pullup current rst = 0.0 v ? 10 tbd a v dd monitor threshold (v rst-low ) tbd 1.95 tbd v v dd monitor threshold (v rst-high ) tbd 2.3 tbd v missing clock detector timeout time from last system clock ris- ing edge to reset initiation, vdd = 2.5 v tbd 350 650 s reset time delay delay between release of any reset source and code execu- tion at location 0x0000 tbd ? ? s minimum rst low time to gener- ate a system reset tbd ? ? s v dd monitor supply current ?1.1tbd a v dd ramp time v dd = 0 v to v dd = v rst v ?? 1 ms
rev. 0.8 135 C8051F410/1/2/3 16. flash memory on-chip, re-programmable flash memory is included for program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx write instruction. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operations is not required. code execution is stalled during flash write/erase operations. refer to ta b l e 16.2 for complete flash memory electrical characteristics. 16.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon laboratories or a third party vendor. this is the only means for programming a non-initialized device. for details on the c2 commands to program flash memory, see section ?26. c2 interface? on page 265 . for detailed guidelines on writing or erasing flash from firmware, please see section ?16.4. flash write and erase guidelines? on page 139 . to ensure the integrity of the flash contents, the on-chip vdd monitor must be enabled to the higher setting (vdmlvl = '1') in any system that includes code that writes and/or erases flash memory from software. furthermore, there should be no delay between enabling the v dd monitor and enabling the v dd monitor as a reset source. any attempt to write or erase flash memory while the v dd monitor disabled will cause a flash error device reset. 16.1.1. flash lock and key functions flash writes and erases by user software are protected with a lock and key function. the flash lock and key register (flkey) must be written with the correct key codes, in sequence, before flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of order, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be written again before a following flash operation can be per - formed. the flkey register is detailed in sfr definition 16.2 . 16.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instruction with the address and data byte to be programmed provided as normal operands . before writing to flash memory using movx, flash write operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be progr ammed should be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). step 2. write the first key code to flkey: 0xa5. step 3. write the second key code to flkey: 0xf1. step 4. set the psee bit (register psctl). step 5. set the pswe bit (register psctl). step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. step 7. clear the pswe and psee bits. step 8. re-enable interrupts.
C8051F410/1/2/3 136 rev. 0.8 16.1.3. flash write procedure bytes in flash memory can be written one byte at a time, or in groups of two. the flbwe bit in register pfe0cn ( sfr definition 13.1 ) controls whether a single byte or a block of two bytes is written to flash during a write operation. when flbwe is cleared to ?0?, the flash will be written one byte at a time. when flbwe is set to ?1?, the flash will be written in two-byte blocks. block writes are performed in the same amount of time as single-byte writes, which can save time when storing large amounts of data to flash memory. during a single-byte write to flash, bytes are written individually, and a flash write will be performed after each movx write instruction. the recommended procedure for writing flash in single bytes is: step 1. disable interrupts. step 2. clear the flbwe bit (register pfe0cn) to select single-byte write mode. step 3. write the first key code to flkey: 0xa5. step 4. write the second key code to flkey: 0xf1. step 5. set the pswe bit (register psctl). step 6. clear the psee bit (register psctl). step 7. using the movx instruction, write a single data byte to the desired location within the 512- byte sector. step 8. clear the pswe bit. step 9. re-enable interrupts. steps 3?8 must be repeated for each byte to be written. for block flash writes, the flash write procedure is only performed after the last byte of each block is writ - ten with the movx write instruction. a flash write block is two bytes long, from even addresses to odd addresses. writes must be performed sequentially (i.e. addresses ending in 0b and 1b must be written in order). the flash write will be performed following the movx write that targets the address ending in 1b. if a byte in the block does not need to be updated in flash, it should be written to 0xff. the recommended procedure for writing flash in blocks is: step 1. disable interrupts. step 2. set the flbwe bit (register pfe0cn) to select block write mode. step 3. write the first key code to flkey: 0xa5. step 4. write the second key code to flkey: 0xf1. step 5. set the pswe bit (register psctl). step 6. clear the psee bit (register psctl). step 7. using the movx instruction, write the first data byte to the even block location (ending in 0b). step 8. clear the pswe bit (register psctl). step 9. write the first key code to flkey: 0xa5. step 10. write the second key code to flkey: 0xf1. step 11. set the pswe bit (register psctl). step 12. clear the psee bit (register psctl). step 13. using the movx instruction, write the second data byte to the odd block location (ending in 1b). step 14. clear the pswe bit (register psctl). step 15. re-enable interrupts. steps 3-14 must be repeated for each block to be written.
rev. 0.8 137 C8051F410/1/2/3 16.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instruction. note: movx read instructions always target xram. 16.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash memory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of flash user space offers protection of the flash program memory from access (reads, writes, or erases) by unprotected code or the c2 interface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the 1?s complement number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are ?1?) and locked when any other flash pages are locked (any bit of the lock byte is ?0?). see the example below for an C8051F410. figure 16.1. flash pr ogram memory map security lock byte: 11111 101b 1?s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page) addresses locked: 0x0000 to 0x03ff (first two flash pages) and 0x7c00 to 0x7dff (lock byte page) access limit set according to the flash security lock byte 0x0000 0x3fff lock byte reserved 0x3ffe 0x4000 flash memory organized in 512-byte pages 0x3e00 unlocked flash pages locked when any other flash pages are locked 0x0000 0x7dff lock byte reserved 0x7dfe 0x7e00 0x7c00 unlocked flash pages C8051F410/1 c8051f412/3
C8051F410/1/2/3 138 rev. 0.8 the level of flash security depends on the flash access method. the three flash access methods that can be restricted are reads, writes, and erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. table 16.1 summarizes the flash security features of the 'f41x devices. table 16.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages (except page with lock byte) permitted permitted permitted read, write or erase locked pages (except page with lock byte) not permitted fedr permitted read or write page containing lock byte (if no pages are locked) permitted permitted permitted read or write page containing lock byte (if any page is locked) not permitted fedr permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted fedr permitted erase page containing lock byte (if no pages are locked) permitted fedr fedr erase page containing lock byte - unlock all pages (if any page is locked) only c2de fedr fedr lock additional pages (change '1's to '0's in the lock byte) not permitted fedr fedr unlock individual pages (change '0's to '1's in the lock byte) not permitted fedr fedr read, write or erase reserved area not permitted fedr fedr c2de - c2 device erase (erases all flash pages including the page containing the lock byte) fedr - not permitted; causes flash error device reset (ferror bit in rstsrc is '1' after reset) - all prohibited operations that are performed via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks the page containing the lock byte. - once written to, the lock byte cannot be modified except by performing a c2 device erase. - if user code writes to the lock byte, the lock does not take effect until the next device reset.
rev. 0.8 139 C8051F410/1/2/3 16.4. flash write and erase guidelines any system which contains routines which write or erase flash memory from software involves some risk that the write or erase routines will execute unintentionally if the cpu is operating outside its specified operating range of vdd, system clock frequency, or temperature. this accidental execution of flash modi - fying code can result in alteration of flash memory contents causing a system failure that is only recover - able by re-flashing the code in the device. to help prevent the accidental modification of flash by firmware, the vdd monitor must be enabled and enabled as a reset source on c8051f41x devices for the flash to be successfully modified. if either the vdd monitor or the vdd monitor reset source is not enabled, a flash error device reset will be generated when the firmware attempts to modify the flash. the following guidelines are recommended for any system that contains routines which write or erase flash from code. 16.4.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum vdd rise time specification of 1 ms is met. if the system cannot meet this rise time specification, then add an external vdd brownout circuit to the /rst pin of the device that holds the device in reset until vdd reaches 2.7 v and re-asserts /rst if vdd drops below 2.7 v. 3. keep the on-chip vdd monitor enabled and enable the vdd monitor as a reset source as early in code as possible. this should be the first set of instructions executed after the reset vector. for 'c'-based systems, this will involve modifying the startup code added by the 'c' compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the vdd monitor and enabling the vdd monitor as a reset source. code examples showing this can be found in an201, "writing to flash from firmware", available from the silicon laboratories web site. note: on c8051f41x devices, both the vdd monitor and the vdd monitor reset source must be enabled to write or erase flash without generating a flash error device reset. 4. as an added precaution, explicitly enable the vdd monitor and enable the vdd monitor as a reset source inside the functions that write and erase flash memory. the vdd monitor enable instructions should be placed just after the instruction to set pswe to a '1', but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use direct assignment operators and explicitly do not use the bit-wise operators (such as and or or). for exam - ple, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc register explicitly set the porsf bit to a '1'. areas to check are initialization code which enables other reset sources, such as the missing clock detector or comparator, for example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this.
C8051F410/1/2/3 140 rev. 0.8 16.4.2. 16.4.2 pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a '1'. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one rou - tine in code that sets both pswe and psee both to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a '1'. handle pointer address updates and loop maintenance outside the "pswe = 1; ... pswe = 0;" area. code examples showing this can be found in an201, "writing to flash from firmware", available from the sili - con laboratories web site. 9. disable interrupts prior to setting pswe to a '1' and leave them disabled until after pswe has been reset to '0'. any interrupts posted during the flash write or erase operation will be ser - viced in priority order after the flash operation has been completed and interrupts have been re-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variables in dif - ferent memory areas. 11. add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal address does not result in modification of the flash. 16.4.3. system clock 12. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or use an external cmos clock. 13. if operating from the external oscillator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed.
rev. 0.8 141 C8051F410/1/2/3 sfr definition 16.1. psctl: program store r/w control sfr definition 16.2. flkey: flash lock and key bits7?2: unused: read = 000000b, write = don?t care. bit1: psee: program store erase enable setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the loca- tion addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash memory. rrrrrrr/wr/wreset value - - - - - - psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f bits7?0: flkey: flash lock and key register write: this register provides a lock and key function for flash erasures and writes. flash writes and erases are enabled by writing 0xa5 followed by 0xf1 to the flkey register. flash writes and erases are automatically disabled after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disabled, the flash will be permanently locked from writes or era- sures until the next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7
C8051F410/1/2/3 142 rev. 0.8 16.5. flash read timing on reset, the c8051f41x flash read timing is configured for operation with system clocks up to 25 mhz. if the system clock will not be increased above 25 mhz, then the flash timing registers may be left at their reset value. for every flash read or fetch, the system provides an internal flash read strobe to the flash memory. the flash read strobe lasts for one or two system clock cycles, based on flrt (flscl.4). if the system clock is greater than 25 mhz, the flrt bit must be set to logic 1 , otherwise data read or fetched from flash may not represent the actual contents of flash. when the flash read strobe is asserted, flash memory is active. when it is de-asserted, flash memory is in a low power state. the flash read strobe does not need to be asserted for longer than 80 ns in order for flash reads and fetches to be reliable. for system clocks greater than 12.5 mhz (but less than 25 mhz), the flash read strobe width is limited by the system clock period. for system clocks less than 12.5 mhz, the flash read strobe is limited by a programmable one shot with a default period of 80 ns (1/12.5 mhz). this is a power saving feature that is very beneficial for very slow system clocks (e.g. 32.768 khz where the system clock period is greater than 30,000 ns). for additional power savings, the one shot can be programmed to values less than 80 ns. the one shot can be trimmed according the equation in the oneshot register description in figure 16.4 . the one shot period must not be programmed less than the minimum read cycle time specified in ta b le 16.2 . the recommended procedure for updating flrt or the oneshot period is: step 1. select sysclk to 25 mhz or less. step 2. disable the prefetch engine (pfen = ?0? in pfe0cn register). step 3. clear flrt to ?0? (flscl register). step 4. set the oneshot period bits. step 5. set flrt to ?1? if sysclk > 25 mhz. step 6. enable the prefetch engine (pfen = ?1? in pfe0cn register). sfr definition 16.3. flscl: flash scale bits7?5: reserved. read = 000b. must write 000b. bit 4: flrt: flash read time control. this bit should be programmed to the smallest allowed value, according to the system clock speed. 0: sysclk < 25 mhz (flash read strobe is one system clock). 1: sysclk > 25 mhz (flash read strobe is two system clocks). bits3?0: reserved. read = 0000b. must write 0000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved reserved flrt reserved reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6
rev. 0.8 143 C8051F410/1/2/3 sfr definition 16.4. oneshot: flash oneshot period table 16.2. flash electrical characteristics v dd = 2.0 to 2.75 v; ?40 to +85 oc unless otherwise specified parameter conditions min typ max units flash size C8051F410/1 c8051f412/3 32768* 16384 ?? bytes endurance v dd is 2.2 v or greater 20 k 90 k ? erase/write erase cycle time 16 20 24 ms write cycle time 38 46 57 s read cycle time 40 ? ? ns v dd write/erase operations 2.25 ? ? v *note: 512 bytes at addresses 0x7e00 to 0x7fff are reserved. bits7?4: unused. read = 0000b. write = don?t care. bits3?0: period: oneshot period control bits. these bits limit the internal flash read strobe width as follows. when the flash read strobe is de-asserted, the flash memory enters a low-power state for the remainder of the system clock cycle. these bits have no effect when the system clocks is greater than 12.5 mhz and flrt = 0. rrrrr/wr/wr/wr/wreset value - - - - period 00001111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaf flash rdmax 5 ns period 5 ns () + =
C8051F410/1/2/3 144 rev. 0.8 n otes :
rev. 0.8 145 C8051F410/1/2/3 17. external ram the c8051f41x devices include 2048 bytes of ram mapped into the external data memory space. all of these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if the movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is provided by the external mem - ory interface control register (emi0cn as shown in sfr definition 17.1 ). note: the movx instruction is also used for writes to the flash memory. see section ?16. flash memory? on page 135 for details. the movx instruction accesses xram by default. for a 16-bit movx operation (@dptr), the upper 5-bits of the 16-bit external data memory address word are "don't cares.? as a result, the ram is mapped modulo style over the entire 64 k external data memory address range. for example, the xram byte at address 0x0000 is shadowed at addresses 0x0800, 0x1000, 0x1800, 0x2000, etc. this is a useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when reaching the ram block boundary. sfr definition 17.1. emi0cn: external memo ry interface control bits 7?3: unused. read = 00000b. write = don?t care. bits 2?0: pgsel: xram page select. the emi0cn register provides the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. since the upper (unused) bits of the register are always zero, the pgsel determines which page of xram is accessed. for example: if emi0cn = 0x01, addresses 0x0100 through 0x01ff will be accessed. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - pgsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaa
C8051F410/1/2/3 146 rev. 0.8 n otes :
rev. 0.8 147 C8051F410/1/2/3 18. port input/output digital and analog resources are available through up to 24 i/o pins. port pins are organized as three byte- wide ports. each of the port pins can be defined as general-purpose i/o (gpio) or analog input/output; port pins p0.0 - p2.7 can be assigned to one of the internal digital resources as shown in figure 18.3 . the designer has complete control over which functions are assigned, limited only by the number of physical i/o pins. this resource assignment flexibility is achieved through the use of a priority crossbar decoder. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital resources to the i/o pins based on the peripheral priority order of the priority decoder ( figure 18.3 and figure 18.4 ). the registers xbr0 and xbr1, defined in sfr definition 18.1 and sfr definition 18.2 , are used to select internal digital functions. port i/os on p0 are 5 v tolerant over the operating range of v io . port i/os on p1 and p2 should not be driven above v io or they will sink current. figure 18.2 shows the port cell circuit. the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1,2). complete electrical specifications for port i/o are given in ta b l e 18.1 on page 163 . figure 18.1. port i/o functional block diagram xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0. 0 p0. 7 8 p0mask, p0match p1mask, p1match registers uart (internal digital signals) h ighest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi 4 p1 i/o cells p1. 0 p1. 7 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 i/o cell p2 (p2.0-p2.7) 8 8 p2. 0 p2. 7 pnmdout, pnmdin registers p2.3?2.6 available on C8051F410/2
C8051F410/1/2/3 148 rev. 0.8 figure 18.2. port i/o cell block diagram gnd /port-outenable port-output push-pull vio vio /weak-pullup (weak) port pad analog input analog select port-input
rev. 0.8 149 C8051F410/1/2/3 18.1. priority crossbar decoder the priority crossbar decoder (figure 18.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the least-significant unassigned port pin is assigned to that resource (excluding uart0, which will be assigned to pins p0.4 and p0.5). if a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pnskip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p1.0 and/or p1.1 for the external oscillator, p1.2 for v ref , p0.6 for the external cnvstr signal, p0.0 for ida0, p0.1 for ida1, and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. figure 18.3 shows the crossbar decoder priority with no port pins skipped (p0skip, p1skip, p2skip = 0x00); figure 18.4 shows the crossbar decoder priority with the xtal1 (p1.0) and xtal2 (p1.1) pins skipped (p1skip = 0x03). figure 18.3. crossbar priority decoder with no pins skipped i0 i1 cnvstr x1 x2 vref 0123456701 2 3456701234567 (*4-w ire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 0000000000 0 0000000000000 sda p0skip[0:7] scl rx0 sf signals pin i/o tx0 nss* sck miso mosi p2 p2skip[0:7] p0 p1 p1skip[0:7]
C8051F410/1/2/3 150 rev. 0.8 figure 18.4. crossbar priority decoder with crystal pins skipped registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assigns both pins associated with the smbus (sda and scl); when the uart is selected, the crossbar assigns both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purposes: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously starting at p0.0 after prioritized functions and skipped pins are assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, depending on the state of the nssmd1-nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. i0 i1 cnvstr x1 x2 vref 012345670123456701234567 (*4-w ire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 000000001100000000000000 p2 p0skip[0:7] p1skip[0:7] = 0x03 p2skip[0:7] tx0 pin i/o scl p0 rx0 sf signals special function signals are not assigned by the crossbar. w hen these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially assignable to peripheral nss* p1 sda sf signals sck miso mosi
rev. 0.8 151 C8051F410/1/2/3 18.2. port i/o initialization port i/o initialization consists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). if the pin is in analog mode, a '1' must also be written to the corresponding port latch. step 2. select the output mode (open-drain or push-pull) for all port pins, using the port output mode register (pnmdout). step 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). step 4. assign port pins to desired peripherals using the xbrn registers. step 5. enable the crossbar (xbare = ?1?). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended. additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all port pins in analog mode must have a '1' set in the corresponding port latch register. all pins default to digital inputs on reset. see sfr definition 18.4 for the pnmdin register details. important note: port 0 pins are 5 v tolerant across the operating range of v io . figure 18.5 shows the input current range of p0 pins when overdriven above v io (when v io is 3.3 v nominal). there are two over - drive modes for port 0: normal and high-impedance. when the corresponding bit in p0oden is logic 0, normal overdrive mode is selected and the port pin requires 150 a peak overdrive current when its volt - age reaches approximately v io + 0.7 v. when the corresponding bit in p0oden is logic 1, high-imped - ance overdrive mode is selected and the port pin does not require any additional overdrive current. pins configured to high-impedance overdrive mode consume slightly more power from v io than pins config - ured to normal overdrive mode. note that port 1 and port 2 pins cannot be overdriven above v io and have the same behavior as p0 in normal mode.
C8051F410/1/2/3 152 rev. 0.8 figure 18.5. port 0 input overdrive current range the output driver characteristics of the i/o pins are defined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bit in xbr1 is ?0?, a weak pullup is enabled for all port i/o con - figured as open-drain. weakpud does not affect the push-pull port i/o. furthermore, the weak pullup is turned off on an output that is driving a ?0? and for pins configured for analog input mode to avoid unneces - sary power dissipation. registers xbr0 and xbr1 must be loaded with the appropriate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can determine the i/o pin-out using the priority decode table. the crossbar must be enabled to use port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled. + - v test i vtest v dd i vtest ( a) v test (v ) 0 -10 -150 v io v io +0.7 i/o cell p0.x pin v io i vtest ( a) v test (v ) 0 10 v io -0.2 v io +0.2 -10 normal mode p0oden.x = 0 high-impedance mode p0oden.x = 1
rev. 0.8 153 C8051F410/1/2/3 sfr definition 18.1. xbr0: port i/o crossbar register 0 bit7: cp1ae: comparator1 asynchronous output enable 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. bit6: cp1e: comparator1 output enable 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. bit5: cp0ae: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. bit4: cp0e: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit3: syscke: /sysclk output enable 0: /sysclk unavailable at port pin. 1: /sysclk output routed to port pin. bit2: smb0e: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. bit1: spi0e: spi i/o enable 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. bit0: urt0e: uart i/o output enable 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe1
C8051F410/1/2/3 154 rev. 0.8 sfr definition 18.2. xbr1: port i/o crossbar register 1 18.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. ports p0-p2 are accessed through corresponding special function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value written to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the exception to this is the execution of the read-modify-write instructions that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an individual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. in addition to performing general purpose i/o, p0 and p1 can generate a port match event if the logic lev - els of the port?s input pins match a software controlled value. a port match event is generated if (p0 & p0mask) does not equal (p0match & p0mask) or if (p1 & p1mask) does not equal bit7: weakpud: port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured as analog input). 1: weak pullups disabled. bit6: xbare: crossbar enable. 0: crossbar disabled. 1: crossbar enabled. bit5: t1e: t1 enable 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit4: t0e: t0 enable 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit3: ecie: pca0 external counter input enable 0: eci unavailable at port pin. 1: eci routed to port pin. bits2?0: pca0me: pca module i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, cex4 routed to port pins. 110: cex0, cex1, cex2, cex3, cex4, cex5 routed to port pins. 111: reserved. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare t1e t0e ecie pca0me 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2
rev. 0.8 155 C8051F410/1/2/3 (p1match & p1mask). this allows software to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. a port match event can cause an interrupt if emat (eie2.1) is set to '1' or cause the internal oscillator to awaken from suspend mode. see section ? 19.1.1. internal oscillator suspend mode ? on page 166 for more information. sfr definition 18.3. p0: port0 sfr definition 18.4. p0mdin: port0 input mode bits7?0: p0.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p0mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p0mdin. directly reads port pin when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x80 bits7?0: analog input configuration bits for p0.7?p0.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured as an analog input. in order for the p0.n pin to be in analog input mode, there must be a '1' in the port latch register corresponding to that pin. 1: corresponding p0.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf1
C8051F410/1/2/3 156 rev. 0.8 sfr definition 18.5. p0mdout: port0 output mode sfr definition 18.6. p0skip: port0 skip bits7?0: output configuration bits for p0.7?p0.0 (respectively): ignored if corresponding bit in regis- ter p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. (note: when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4 bits7?0: p0skip[7:0]: port0 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd4
rev. 0.8 157 C8051F410/1/2/3 sfr definition 18.7. p0mat: port0 match sfr definition 18.8. p0mask: port0 mask sfr definition 18.9. p0oden: port0 overdrive mode bits7?0: p0mat[7:0]: port0 match value. these bits control the value that unmasked p0 port pins are compared against. a port match event is generated if (p0 & p0mask) does not equal (p0mat & p0mask). r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd7 bits7?0: p0mask[7:0]: port0 mask value. these bits select which port pins will be compared to the value stored in p0mat. 0: corresponding p0.n pin is ignored and cannot cause a port match event. 1: corresponding p0.n pin is compared to the corresponding bit in p0mat. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc7 bits7?0: high impedance overdrive mode enable bits for p0.7?p0.0 (respectively). port pins configured to high-impedance overdrive mode do not require additional overdrive current, although selecting this mode results in a slight increase in supply current. port pins configured to normal overdrive mode require approximately 150 a of input overdrive cur- rent when the voltage at the pin reaches v io +0.7 v. 0: corresponding p0.n pin is configured to normal overdrive mode. 1: corresponding p0.n pin is configured to high-impedance overdrive mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb0
C8051F410/1/2/3 158 rev. 0.8 sfr definition 18.10. p1: port1 sfr definition 18.11. p1mdin: port1 input mode bits7?0: p1.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p1mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p1mdin. directly reads port pin when configured as digital input. 0: p1.n pin is logic low. 1: p1.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x90 bits7?0: analog input configuration bits for p1.7?p1.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured as an analog input. in order for the p1.n pin to be in analog input mode, there must be a '1' in the port latch register corresponding to that pin. 1: corresponding p1.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf2
rev. 0.8 159 C8051F410/1/2/3 sfr definition 18.12. p1mdout: port1 output mode sfr definition 18.13. p1skip: port1 skip bits7?0: output configuration bits for p1.7?p1.0 (respectively): ignored if corresponding bit in regis- ter p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa5 bits7?0: p1skip[7:0]: port1 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd5
C8051F410/1/2/3 160 rev. 0.8 sfr definition 18.14. p1mat: port1 match sfr definition 18.15. p1mask: port1 mask bits7?0: p1mat[7:0]: port1 match value. these bits control the value that unmasked p0 port pins are compared against. a port match event is generated if (p1 & p1mask) does not equal (p1mat & p1mask). r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcf bits7?0: p1mask[7:0]: port1 mask value. these bits select which port pins will be compared to the value stored in p1mat. 0: corresponding p1.n pin is ignored and cannot cause a port match event. 1: corresponding p1.n pin is compared to the corresponding bit in p1mat. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbf
rev. 0.8 161 C8051F410/1/2/3 sfr definition 18.16. p2: port2 sfr definition 18.17. p2mdin: port2 input mode bits7?0: p2.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p2mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p2mdin. directly reads port pin when configured as digital input. 0: p2.n pin is logic low. 1: p2.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xa0 bits7?0: analog input configuration bits for p2.7?p2.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured as an analog input. in order for the p2.n pin to be in analog input mode, there must be a '1' in the port latch register corresponding to that pin. 1: corresponding p2.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf3
C8051F410/1/2/3 162 rev. 0.8 sfr definition 18.18. p2mdout: port2 output mode sfr definition 18.19. p2skip: port2 skip bits7?0: output configuration bits for p2.7?p2.0 (respectively): ignored if corresponding bit in regis- ter p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. rrrrrrrr/wreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa6 bits7?0: p2skip[7:0]: port2 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd6
rev. 0.8 163 C8051F410/1/2/3 table 18.1. port i/o dc electrical characteristics v io = 2.0 to 5.25 v, ?40 to +85 c unless otherwise specified parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?70 a, port i/o push-pull v io ? tbd v io ? tbd ? ? ? ? v output low voltage v io = 2.0 v: i ol = 70 a i ol = 8.5 ma v io = 4.0 v: i ol = 70 a i ol = 8.5 ma ? ? ? ? ? ? ? ? 50 750 40 400 mv input high voltage v io x tbd ??v input low voltage ? ? v io x tbd v input leakage current weak pullup off ? < 0.1 tbd a weak pullup impedance ? 100 ? k ?
C8051F410/1/2/3 164 rev. 0.8 n otes :
rev. 0.8 165 C8051F410/1/2/3 19. oscillators c8051f41x devices include a programmable internal oscillator, an external oscillator drive circuit, and a clock multiplier. the internal oscillator can be enabled/disabled and calibrated using the oscicn and oscicl registers, as shown in figure 19.1 . the system clock (sysclk) can be derived from the internal oscillator, external oscillator circuit, or smartclock oscillator. the clock multiplier can produce three possi - ble base outputs which can be scaled by a programmable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7: internal oscillator x 2, external oscillator x 2, or external oscillator x 4. oscillator electrical specifica - tions are given in ta b l e 19.1 on page 175 . figure 19.1. oscillator diagram 19.1. programmable internal oscillator all c8051f41x devices include a programmable internal oscillator that defaults as the system clock after a system reset. the internal oscillator period can be programmed via the oscicl register, shown in sfr definition 19.2 . on c8051f41x devices, oscicl is factory calibrated to obtain a 24.5 mhz frequency. electrical specifications for the precision internal oscillator are given in table 19.1 on page 175. note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or 128 as defined by the ifcn bits in register oscicn. the divide value defaults to 128 following a reset. clock multiplier osc exosc input circuit xtlvld xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clkmul mulen mulinit mulrdy mulsel1 mulsel0 programmable internal clock generator en oscicl oscicn ioscen ifrdy suspend ifcn1 ifcn0 iosc exosc / 2 x4 exosc iosc/2 sysclk clksel clksl1 clksl0 n n smartclock oscillator ifcn2 iosc muldiv2 muldiv1 muldiv0
C8051F410/1/2/3 166 rev. 0.8 19.1.1. internal oscillator suspend mode when software writes a logic 1 to suspend (oscicn.5), the internal oscillator is suspended. if the sys - tem clock is derived from the internal oscillator, the input clock to the peripheral or cip-51 will be stopped until one of the following events occur: port 0 match event. port 1 match event. comparator 0 enabled and output is logic 0. comparator 1 enabled and output is logic 0. smartclock oscillator fail event. smartclock alarm event. when one of the internal oscillator awakening events occur, the internal oscillator, cip-51, and affected peripherals resume normal operation, regardless of whether the event also causes an interrupt. the cpu resumes execution at the instruction following the write to suspend.
rev. 0.8 167 C8051F410/1/2/3 sfr definition 19.1. oscicn: internal oscillator control sfr definition 19.2. oscicl: internal oscillator calibration bit7: ioscen: internal oscillator enable bit. 0: internal oscillator disabled. 1: internal oscillator enabled. bit6: ifrdy: internal oscillator frequency ready flag. 0: internal oscillator is not running at programmed frequency. 1: internal oscillator is running at programmed frequency. bit5: suspend: internal oscillator suspend enable bit. setting this bit to logic 1 places the internal oscillator in suspend mode. the internal oscil- lator resumes operation when one of the suspend mode awakening events occur. bits4?3: unused. read = 00b, write = don't care. bits2?0: ifcn2?0: internal oscillator frequency control bits. 000: sysclk derived from internal oscillator divided by 128 (default). 001: sysclk derived from internal oscillator divided by 64. 010: sysclk derived from internal oscillator divided by 32. 011: sysclk derived from internal oscillator divided by 16. 100: sysclk derived from internal oscillator divided by 8. 101: sysclk derived from internal oscillator divided by 4. 110: sysclk derived from internal oscillator divided by 2. 111: sysclk derived from internal oscillator divided by 1. r/w r r/w r r r/w r/w r/w reset value ioscen ifrdy suspend - - ifcn2 ifcn1 ifcn0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2 bit7: unused. read = 0. write = don?t care. bits 6?0: oscicl: internal oscillator calibration register. this register determines the internal oscillator period. on c8051f41x devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 mhz. r r/w r/w r/w r/w r/w r/w r/w reset value -osciclvaries bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb3
C8051F410/1/2/3 168 rev. 0.8 19.2. external oscillator drive circuit the external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or rc network. a cmos clock may also provide a clock input. for a crystal or ceramic resonator configuration, the crys - tal/resonator must be wired across the xtal1 and xtal2 pins as shown in option 1 of figure 19.1 . a 10 m ? resistor also must be wired across the xtal1 and xtal2 pins for the crystal/resonator configura - tion. in rc, capacitor, or cmos clock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 19.1 . the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 19.3. oscxcn: external oscillator control ). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive circuit is enabled in crystal/resonator mode, port pins p1.0 and p1.1 are used as xtal1 and xtal2 respectively. when the external oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p1.1 is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by the oscillator circuit; see section ?18.1. priority cross - bar decoder? on page 149 for crossbar configuration. additionally, when using the external oscillator cir - cuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs (with ?1's in the corresponding port latch). in cmos clock mode, the associated pin should be con - figured as a digital input . see section ?18.2. port i/o initialization? on page 151 for details on port input mode selection. the frequency of the external oscillator can be measured with respect to the smartclock oscillator using timer 2 or timer 3. section ? 24.2.3. external/smartclock capture mode ? on page 241 shows how this can be accomplished. 19.2.1. clocking timers directly through the external oscillator the external oscillator source divided by eight is a clock option for the timers ( section ?24. timers? on page 231 ) and the programmable counter array (pca) ( section ?25. programmable counter array (pca0)? on page 249 ). when the external oscillator is used to clock these peripherals, but is not used as the system clock, the external oscillator frequency must be less than or equal to the system clock fre - quency. in this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized with the system clock; the jitter associated with this synchronization is limited to 0.5 system clock cycles. 19.2.2. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 19.1 , option 1. the external oscillator frequency control value (xfcn) should be chosen from the crystal column of the table in sfr definition 19.3 . for example, a 12 mhz crys - tal requires an xfcn setting of 111b.
rev. 0.8 169 C8051F410/1/2/3 when the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time to achieve proper bias. introducing a delay of 1 ms between enabling the oscillator and checking the xtlvld bit will prevent a premature switch to the external oscillator as the system clock. switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. the rec - ommended procedure is: step 1. force the xtal1 and xtal2 pins low by writing 0's to the port latch. step 2. configure xtal1 and xtal2 as analog inputs. step 3. release the crystal pins by writing ?1's to the port latch. step 4. enable the external oscillator. step 5. wait at least 1 ms. step 6. poll for xtlvld => '1'. step 7. switch the system clock to the external oscillator. note: tuning-fork crystals may require additional settling time before xtlvld returns a valid result. the capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: the load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 19.1 , option 1. the total value of the capacitors and the stray capac - itance of the xtal pins should equal 25 pf. with a stray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 19.2 . figure 19.2. 32.768 khz external crystal example important note on external crystals: crystal oscillator circuits are quite sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. 22 pf 22 pf 32.768 khz 10 m xtal1 xtal2 ?
C8051F410/1/2/3 170 rev. 0.8 19.2.3. external rc example if an rc network is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 19.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscillator frequency control value (xfcn) in the oscxcn register, first select the rc network value to produce the desired frequency of oscillation. if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 19.3, the required xfcn setting is 010b. programming xfcn to a higher setting in rc mode will improve frequency accuracy at a slightly increased external oscillator supply current. 19.2.4. external capacitor example if a capacitor is used as an external oscillator for the mcu, the circuit should be configured as shown in figure 19.1 , option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to determine the required external oscillator frequency control value (xfcn) in the oscxcn register, select the fre - quency of oscillation and calculate the capacitance to be used from the equations below. assume v dd = 2.0 v and f = 75 khz: f = kf / (c x v dd ) 0.075 mhz = kf / (c x 2.0) since the frequency of roughly 75 khz is desired, select the k factor from the table in sfr definition 19.3 as kf = 7.7: 0.075 mhz = 7.7 / (c x 2.0) c x 2.0 = 7.7 / 0.075 mhz c = 102.6 / 2.0 pf = 51.3 pf therefore, the xfcn value to use in this example is 010b.
rev. 0.8 171 C8051F410/1/2/3 sfr definition 19.3. oscxcn: external oscillator control bit7: xtlvld: crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits6?4: xoscmd2?0: external oscillator mode bits. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = 0b; must write 0b. bits2?0: xfcn2?0: external oscillator frequency control bits. 000-111: see table below: crystal mode (circuit from figure 19.1, option 1; xoscmd = 11x) choose xfcn value to match crystal or resonator frequency. rc mode (circuit from figure 19.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 ) / (r x c) , where f = frequency of clock in mhz c = capacitor value in pf r = pullup resistor value in k ? c mode (circuit from figure 19.1, option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf / (c x v dd ) , where f = frequency of clock in mhz c = capacitor value the xtal2 pin in pf v dd = power supply on mcu in volts r r/w r/w r/w r/w r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd0 reserved xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb1 xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f 20 khz f 25 khz k factor = 0.87 001 20 khz < f 58 khz 25 khz < f 50 khz k factor = 2.6 010 58 khz < f 155 khz 50 khz < f 100 khz k factor = 7.7 011 155 khz < f 415 khz 100 khz < f 200 khz k factor = 22 100 415 khz < f 1.1 mhz 200 khz < f 400 khz k factor = 65 101 1.1 mhz < f 3.1 mhz 400 khz < f 800 khz k factor = 180 110 3.1 mhz < f 8.2 mhz 800 khz < f 1.6 mhz k factor = 664 111 8.2 mhz < f 25 mhz 1.6 mhz < f 3.2 mhz k factor = 1590
C8051F410/1/2/3 172 rev. 0.8 19.3. clock multiplier the clock multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro - grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. the clock multiplier?s input can be selected from the external oscillator, or the internal or external oscillators divided by 2. this produces three possible base outputs which can be scaled by a programmable factor: internal oscillator x 2, external oscillator x 2, or external oscillator x 4. see section 19.4 for details on system clock selection. the clock multiplier is configured via the clkmul register (sfr definition 19.4). the procedure for con - figuring and enabling the clock multiplier is as follows: 1. reset the multiplier by writing 0x00 to register clkmul. 2. select the multiplier input source via the mulsel bits. 3. select the multiplier output scaling factor via the muldiv bits 4. enable the multiplier with the mulen bit (clkmul | = 0x80). 5. delay for >5 s. 6. initialize the multiplier with the mulinit bit (clkmul | = 0xc0). 7. poll for mulrdy => ?1?. important note: when using an external oscillator as the input to the clock multiplier, the external source must be enabled and stable before the multiplier is initialized. see section 19.4 for details on selecting an external oscillator source. the clock multiplier allows faster operation of the cip-51 core and is intended to generate an output fre - quency between 25 and 50 mhz. the clock multiplier can also be used with slow input clocks. however, if the clock is below the minimum clock multiplier input frequency (fcm min ) specified in ta b le 19.1 , the gen - erated clock will consist of four fast pulses followed by a long delay until the next input clock rising edge. the average frequency of the output is equal to 4x the input, but the instantaneous frequency may be faster. see figure 19.3 for more information. figure 19.3. example cl ock multiplier output if f cm > f cm min in f cm in f cm out if f cm < f cm min in f cm out f cm in
rev. 0.8 173 C8051F410/1/2/3 sfr definition 19.4. clkmul: clock multiplier control bit7: mulen: clock multiplier enable 0: clock multiplier disabled. 1: clock multiplier enabled. bit6: mulinit: clock multiplier initialize this bit should be a ?0? when the clock multiplier is enabled. once enabled, writing a ?1? to this bit will initialize the clock multiplier. the mulrdy bit reads ?1? when the clock multiplier is stabilized. bit5: mulrdy: clock multiplier ready this read-only bit indicates the status of the clock multiplier. 0: clock multiplier not ready. 1: clock multiplier ready (locked). bits4?2: muldiv: clock multiplier output scaling factor these bits scale the clock multiplier output. 000: clock multiplier output scaled by a factor of 1. 001: clock multiplier output scaled by a factor of 1. 010: clock multiplier output scaled by a factor of 1. 011: clock multiplier output scaled by a factor of 2/3*. 100: clock multiplier output scaled by a factor of 2/4 (or 1/2). 101: clock multiplier output scaled by a factor of 2/5*. 110: clock multiplier output scaled by a factor of 2/6 (or 1/3). 111: clock multiplier output scaled by a factor of 2/7*. *note: the clock multiplier output duty cycle is not 50% for these settings. bits1?0: mulsel: clock multiplier input select these bits select the clock supplied to the clock multiplier. r/w r/w r r/w r/w r/w r/w r/w reset value mulen mulinit mulrdy muldiv mulsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xab mulsel selected input clock clock multiplier output for muldiv = 000b 00 internal oscillator / 2 internal oscillator x 2 01 external oscillator external oscillator x 4 10 external oscillator / 2 external oscillator x 2 11 internal oscillator internal oscillator x 4
C8051F410/1/2/3 174 rev. 0.8 19.4. system clock selection the internal oscillator requires little start-up time and may be selected as the system clock immediately fol - lowing the oscicn write that enables the internal oscillator. external crystals and ceramic resonators typ - ically require a start-up time before they are settled and ready for use. the crystal valid flag (xtlvld in register oscxcn) is set to ?1? by hardware when the external oscillator is settled. to avoid reading a false xtlvld, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking xtlvld. rc and c modes typically require no startup time. the clksl[1:0] bits in register clksel select which oscillator source is used as the system clock. clksl[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter - nal oscillator may still clock certain peripherals (timers, pca) when another oscillator is selected as the system clock. the system clock may be switched on-the-fly between the internal oscillator, external oscilla - tor, smartclock oscillator, and clock multiplier, as long as the selected clock source is enabled and has settled. sfr definition 19.5. clksel: clock select bits7?6: unused. read = 00b; write = don?t care. bits5?4: clkdiv1?0: output /sysclk divide value these bits can be used to pre-divide the /sysclk output before it is sent to a port pin through the crossbar. 00: output will be sysclk. 01: output will be sysclk/2. 10: output will be sysclk/4. 11: output will be sysclk/8. bit3: unused. read = 0b; write = don?t care. bit2: reserved. read = 0b; must write 0b. bits1?0: clksl1?0: system clock select these bits select the system clock source. r r r/w r/w r r/w r/w r/w reset value - - clkdiv - reserved clksl 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa9 clksl selected clock 00 internal oscillator (as determined by the ifcn bits in register oscicn) 01 external oscillator 10 clock multiplier 11 smartclock oscillator
rev. 0.8 175 C8051F410/1/2/3 table 19.1. oscillator electrical characteristics ?40 to +85 c unless otherwise specified parameter conditions min typ max units internal oscillator frequency reset frequency 24 24.5 25 mhz internal oscillator supply current (from v dd ) oscicn.7 = 1 ? 400 ? a minimum clock multiplier input frequency (fcm min ) t = 25 c ? 1.6 ? mhz
C8051F410/1/2/3 176 rev. 0.8 n otes :
rev. 0.8 177 C8051F410/1/2/3 20. smartclock (real time clock) c8051f41x devices include a low power smartclock peripheral (real time clock). the smartclock has a dedicated 32 khz oscillator that can be configured for use with or without a crystal, a 47-bit smartclock timer with alarm, a backup supply regulator and 64 bytes of battery-backed sram. when the backup sup - ply voltage (v rtc-backup ) is powered, the smartclock peripheral remains fully functional if the core sup - ply voltage (v dd ) is lost. the smartclock allows a maximum of 137 year 47-bit independent time-keeping when used with a 32.768 khz watch crystal and backup supply voltage of at least 1v. the switchover logic powers smart - clock from the backup supply when the voltage at v rtc-backup is greater than v dd . the smartclock alarm and missing clock detector can interrupt the cip-51, wake the internal oscillator from suspend mode, or generate a device reset if the smartclock timer reaches a pre-set value or the oscillator stops. figure 20.1. smartclo ck block diagram 64b backup ram smartclock oscillator smartclock cip-51 cpu xtal4 xtal3 switchover logic rtc0cn capturen alarmn rtc0xcn ramdata ramaddr rtc0key rtc0adr rtc0dat interface registers internal registers smartclock state machine interrupt backup regulator v dd v rtc-backup 47-bit smartclock timer
C8051F410/1/2/3 178 rev. 0.8 20.1. smartclock interface the smartclock interface consists of three registers: rtc0key, rtc0adr, and rtc0dat. these inter - face registers are located on the cip-51?s sfr map and provide access to the smartclock internal regis - ters listed in table 20.1 . the smartclock internal registers can only be accessed indirectly through the smartclock interface. 20.1.1. smartclock lock and key functions the smartclock interface is protected with a lock and key function. the smartclock lock and key reg - ister (rtc0key) must be written with the correct key codes, in sequence, before writes and reads to rtc0adr and rtc0dat may be performed. the key codes are: 0xa5, 0xf1. there are no timing restric - tions, but the key codes must be written in order. if the key codes are written out of order, the wrong codes are written, or an invalid read or write is attempted, further writes and reads to rtc0adr and rtc0dat will be disabled until the next system reset. once the smartclock interface is unlocked, software may per - form accesses of the smartclock registers until an invalid access, the interface is locked, or a system reset. reading the rtc0key register at any time will provide the smartclock interface status and will not inter - fere with the sequence that is being written. the rtc0key register description in sfr definition 20.1 lists the definition of each status code. 20.1.2. using rtc0adr and rtc0dat to access smartclock internal registers the smartclock internal registers can be read and written using rtc0adr and rtc0dat. the rtc0adr register selects the smartclock internal register that will be targeted by subsequent reads or writes. prior to each read or write, busy (rtc0adr.7) should be checked to make sure the smartclock interface is not busy performing another read or write operation. a smartclock write operation is initiated by writing to the rtc0dat register. below is an example of writing to a smartclock internal register. step 1. poll busy (rtc0adr.7) until it returns a ?0?. step 2. write 0x06 to rtc0adr. this selects the internal rtc0cn register at smartclock address 0x06. step 3. write 0x00 to rtc0dat. this operation writes 0x00 to the internal rtc0cn register. an smartclock read operation is initiated by setting the smartclock interface busy bit. this transfers the contents of the internal register selected by rtc0adr to rtc0dat. the transferred data will remain in rtc0dat until the next read or write operation. below is an example of reading a smartclock internal register. step 1. poll busy (rtc0adr.7) until it returns a ?0?. step 2. write 0x06 to rtc0adr. this selects the internal rtc0cn register at smartclock address 0x06. step 3. write ?1? to busy. this initiates the transfer of data from rtc0cn to rtc0dat. step 4. poll busy (rtc0adr.7) until it returns a ?0?. step 5. read data from rtc0dat. this data is a copy of the rtc0cn register. note: the rtc0adr and rtc0dat registers will retain their state upon a device reset. 20.1.3. smartclock interface autoread feature when autoread is enabled, each read from rtc0dat initiates the next indirect read operation on the smartclock internal register selected by rtc0adr. software should set the busy bit once at the begin -
rev. 0.8 179 C8051F410/1/2/3 ning of each series of consecutive reads. software must check if the smartclock interface is busy prior to reading rtc0dat. autoread is enabled by setting autord (rtc0adr.6) to logic 1. 20.1.4. rtc0adr autoincrement feature for ease of reading and writing the 48-bit capture and alarm values, rtc0adr automatically incre - ments after each read or write to a capturen or alarmn register. this speeds up the process of setting an alarm or reading the current smartclock timer value. table 20.1. smartclock internal registers smartclock address smartclock register register name description 0x00 - 0x05 capturen smartclock capture registers six registers used for setting the 47-bit smartclock timer or reading its current value. the lsb of capture0 is not used. 0x06 rtc0cn smartclock control register controls the operation of the smartclock state machine. 0x07 rtc0xcn smartclock oscillator control register controls the operation of the smartclock oscillator. 0x08?0x0d alarmn smartclock alarm registers six registers used to set or read the 47-bit smartclock alarm value. the lsb of alarm0 is not used. 0x0e ramaddr smartclock backup ram indirect address register used as an index to the 64 byte smartclock backup ram. 0x0f ramdata smartclock backup ram indirect data register used to read or write the byte pointed to by ramaddr.
C8051F410/1/2/3 180 rev. 0.8 sfr definition 20.1. rtc0key: smartclock lock and key bits 7?0: rtc0state. smartclock state bits read: 0x00: smartclock interface is locked. 0x01: smartclock interface is locked. first key code (0xa5) has been written, waiting for second key code. 0x02: smartclock interface is unlocked. first and second key codes (0xa5, 0xf1) have been written. 0x03: smartclock interface is disabled until the next system reset. write: when rtc0state = 0x00 (locked), writing 0xa5 followed by 0xf1 unlocks the smartclock interface. when rtc0state = 0x01 (waiting for second key code), writing any value other than the second key code (0xf1) will change rtc0state to 0x03 and disable the smartclock interface until the next system reset. when rtc0state = 0x02 (unlocked), any write to rtc0key will lock the smartclock interface. when rtc0state = 0x03 (disabled), writes to rtc0key have no effect. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xae
rev. 0.8 181 C8051F410/1/2/3 sfr definition 20.2. rtc0adr: smartclock address bit 7: busy: smartclock interface busy bit. writing a ?1? to this bit initiates a smartclock indirect read operation. this bit is automati- cally cleared by hardware when the operation is complete. 0: smartclock interface is not busy. 1: smartclock interface is busy performing a read or write operation. bit 6: autord: smartclock interface auto read enable. 0: busy must be written manually for each smartclock indirect read operation. 1: the next smartclock indirect read operation is initiated when rtc0dat is read by soft- ware. bit 5: vregen: backup supply voltage regulator enable. this bit is automatically set to 1b when v rtc-backup > v dd . 0: backup supply voltage regulator disabled (smartclock powered from v dd ). 1: force backup supply voltage regulator enabled (smartclock powered from v rtc- backup ). bit 4: short: short read/write timing enable. 0: smartclock reads and writes are 4 system clocks wide. 1: smartclock reads and writes are 1 system clock wide. note: increasing the speed of the smartclock reads and writes may also slightly increase power consumption. bits 3?0: rtc0addr: smartclock address bits these bits select the smartclock internal register that is targeted by reads/writes to rtc0dat. note: the rtc0addr bits increment after each indirect read/write operation that targets a capturen or alarmn internal register. r/w r/w r/w r/w r/w r/w r/w r/w reset value busy autord vregen short rtc0addr variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xac rtc0addr smartclock internal register 0000 capture0 0001 capture1 0010 capture2 0011 capture3 0100 capture4 0101 capture5 0110 rtc0cn 0111 rtc0xcn 1000 alarm0 1001 alarm1 1010 alarm2 1011 alarm3 1100 alarm4 1101 alarm5 1110 ramaddr 1111 ramdata
C8051F410/1/2/3 182 rev. 0.8 sfr definition 20.3. rtc0dat: smartclock data 20.2. smartclock clocking sources the smartclock peripheral is clocked from its own timebase, independent of sysclk. the rtcclk timebase is derived from the smartclock oscillator circuit. this oscillator has two modes of operation: crystal mode, and self-oscillate mode. the oscillation frequency is 32.768 khz in crystal mode and can be configured to roughly 20 khz or 40 khz in self-oscillate mode. the frequency of the smartclock oscil - lator can be measured with respect to another oscillator using timer 2 or timer 3. section ? 24.2.3. external/smartclock capture mode ? on page 241 shows how this can be accomplished. note: the smartclock clock can be selected as system clock and routed to a port pin. see sfr definition 19.5. ?clksel: clock select? on page 174 and section ? 18. port input/output ? on page 147 . 20.2.1. using the smartclock oscillator in crystal mode when using crystal mode, a 32.768 khz crystal should be connected between xtal3 and xtal4. no other external components are required. the following steps show how to start the smartclock crystal oscillator in software: step 1. set smartclock to crystal mode (xmode = 1). step 2. optional. enable automatic gain control (agcen = 1). step 3. optional. enable smartclock bias doubling (biasx2 = 1). step 4. enable power to the smartclock oscillator circuit (rtc0en = 1). step 5. poll the smartclock clock valid bit (clkvld) until the crystal oscillator stabilizes. step 6. optional . clear biasx2 to ?0? after the oscillator stabilizes to conserve power. 20.2.2. using the smartclock oscillator in self-oscillate mode when using self-oscillate mode, the xtal3 and xtal4 pins should be shorted together. the following steps show how to configure smartclock for use in self-oscillate mode: step 1. set smartclock to self-oscillate mode (xmode = 0). step 2. set the desired oscillation frequency: for oscillation at about 20 khz, set biasx2 = 0. for oscillation at about 40 khz, set biasx2 = 1. step 3. the oscillator starts oscillating instantaneously. note: software should avoid read modify write instructions when writing values to rtc0dat. bits 7?0: rtc0dat. smartclock data bits holds data transferred to/from the internal smartclock register selected by rtc0adr. r/w r/w r/w r/w r/w r/w r/w r/w reset value variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xad
rev. 0.8 183 C8051F410/1/2/3 20.2.3. automatic gain control (crystal mode only) automatic gain control is enabled by setting agcen (rtc0xcn.7) to a logic 1. when enabled, the smartclock oscillator trims the oscillation amplitude to save power. this mode is useful for preserving battery life in systems where oscillator performance is not critical and external conditions are stable. note: setting the agcen to a logic 1 in self-oscillator mode can lead to drastic changes in the smart - clock oscillator frequency. 20.2.4. smartclock bias doubling the smartclock bias doubling is enabled by setting biasx2 (rtc0xcn.5) to 1b. when enabled, the bias current to smartclock is doubled allowing for more robust oscillator performance. when the smart - clock oscillator is in self-oscillate mode, the oscillation frequency is increased from 20 to 40 khz. when operating in crystal mode, the oscillator is less likely to be affected by external conditions when biasx2 = ?1?. enabling bias doubling increases the power consumption of smartclock; therefore, it is not recommended for use in power-critical systems. 20.2.5. smartclock missing clock detector the smartclock missing clock detector is a one-shot circuit enabled by setting mclken (rtc0cn.6) to a logic 1. when the smartclock missing clock detector is enabled, oscfail (rtc0cn.5) is set by hard - ware if rtcclk remains high or low for more than 50 s. a smartclock missing clock detector timeout triggers three events: 1. awakening the internal oscillator from suspend mode. 2. smartclock interrupt (if the smartclock interrupt is enabled). 3. mcu reset (if smartclock is enabled as a reset source). note: the smartclock missing clock detector should be disabled when making changes to the oscillator settings in rtc0xcn.
C8051F410/1/2/3 184 rev. 0.8 internal register definition 20.4. rtc0cn: smartclock control bit 7: rtc0en: smartclock enable bit. 0: smartclock bias and crystal oscillator disabled. smartclock is powered from v dd only. 1: smartclock bias and crystal oscillator enabled. smartclock can switch to the backup battery if v dd fails. bit 6: mclken: smartclock missing clock detector enable bit. when enabled, the smartclock missing clock detector sets the oscfail bit if the smart- clock clock frequency falls below approximately 20 khz. 0: smartclock missing clock detector disabled. 1: smartclock missing clock detector enabled. bit 5: oscfail: smartclock clock fail flag. set by hardware when a missing clock detector timeout occurs. when the smartclock interrupt is enabled, setting this bit causes the cpu to vector to the smartclock interrupt service routine. this bit is not automatically cleared by hardware. bit 4: rtc0tr: smartclock timer run control. 0: smartclock timer holds its current value. 1: smartclock timer increments every smartclock clock period. bit 3: rtc0aen: smartclock alarm enable. 0: smartclock alarm events disabled. 1: smartclock alarm events enabled. bit 2: alrm: smartclock alarm event flag. set by hardware when the smartclock timer value is greater than or equal to the value of the alarmn registers. when the smartclock interrupt is enabled, setting this bit causes the cpu to vector to the smartclock interrupt service routine. this bit is not automatically cleared by hardware. bit 1: rtc0set: smartclock set bit. writing a ?1? to this bit causes the 47-bit value in capturen registers to be transferred to the smartclock timer. this bit is automatically cleared by hardware once the transfer is complete. bit 0: rtc0cap: smartclock capture bit. writing a ?1? to this bit causes the 47-bit smartclock timer value to be transferred to the capturen registers. this bit is automatically cleared by hardware once the transfer is complete. r/w r/w r/w r/w r/w r/w r/w r/w reset value rtc0en mclken oscfail rtc0tr rtc0aen alrm rtc0set rtc0cap variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smartclock address: note: this register is not an sfr. it can only be accessed indirectly through rtc0adr and rtc0dat. 0x06
rev. 0.8 185 C8051F410/1/2/3 internal register definition 20.5. rtc0xcn: smartclock oscillator control 20.3. smartclock time r and alarm function the smartclock timer is a 47-bit counter that, when running (rtc0tr = 1), is incremented every rtc - clk cycle. the timer has an alarm function that can be set to generate an interrupt, reset the mcu, or release the internal oscillator from suspend mode at a specific time. 20.3.1. setting and reading the smartclock timer value the 47-bit smartclock timer can be set or read using the six capturen internal registers. note that the timer does not need to be stopped before reading or setting its value. the following steps can be used to set the timer value: step 1. write the desired 47-bit set value to the capturen registers (the lsb of capture0 is not used). step 2. write ?1? to rtc0set. this will transfer the contents of the capturen registers to the timer. step 3. operation is complete when rtc0set is cleared to ?0? by hardware. bit 7: agcen: crystal oscillator automatic gain control enable bit (crystal mode only). 0: automatic gain control disabled. 1: automatic gain control enabled. bit 6: xmode: smartclock mode select bit. this bit selects whether smartclock will be used with or without a crystal. 0: smartclock is configured to self-oscillate mode. 1: smartclock is configured to crystal mode. bit 5: biasx2: smartclock bias double enable bit. 0: smartclock bias current doubling is disabled. 1: smartclock bias current doubling is enabled. bit 4: clkvld: smartclock clock valid bit. set by hardware when the smartclock crystal oscillator is nearly stable. this bit always reads 1b when smartclock is used in self-oscillate mode (xmode = 0). this bit should be checked at least 1 ms after enabling the smartclock oscillator circuit and should not be used for an oscillator fail detect (use oscfail in rtc0cn instead). bits 3?1: unused. read = 000b. write = don?t care. bit 0: vbaten: smartclock v bat indicator. note: this bit always reads 1b when smartclock is disabled (rtc0en = 0). for smartclock enabled (rtc0en = 1): 0: smartclock is powered from v dd . 1: smartclock is powered from the v rtc-backup supply. r/w r/w r/w r r r r r reset value agcen xmode biasx2 clkvld - - - vbaten variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smartclock address: note: this register is not an sfr. it can only be accessed indirectly through rtc0adr and rtc0dat. 0x07
C8051F410/1/2/3 186 rev. 0.8 the following steps can be used to read the current timer value: step 1. write ?1? to rtc0cap. this will transfer the contents of the timer to the capturen registers (the lsb of the smartclock timer will be found in capture0.1). step 2. poll rtc0cap until it is cleared to ?0? by hardware. step 3. a snapshot of the timer value can be read from the capturen registers 20.3.2. setting a smartclock alarm the smartclock alarm function compares the 47-bit value of smartclock timer to the value of the alarmn registers. an alarm event is triggered if the smartclock timer is greater than or equal to the alarmn registers. if the smartclock interrupt is enabled, the cip-51 will vector to the smartclock inter - rupt service routine when an alarm event occurs. if smartclock is enabled as a reset source, the mcu will be reset when an alarm event occurs. also, the internal oscillator will awaken from suspend mode on a smartclock alarm event. the following steps can be used to set up a smartclock alarm: step 1. disable smartclock alarm events (rtc0aen = 0). step 2. set the alarmn registers to the desired value. step 3. enable smartclock alarm events (rtc0aen = 1). note: when an alarm event occurs and smartclock interrupts are enabled, software should clear the alrm bit and set the alarm5-0 registers to the maximum possible value to avoid continuous alarm inter - rupts. internal register definition 20.6. capturen: smartclock timer capture bits 7?0: capturen: smartclock set/capture value. these 6 registers (capture5?capture0) are used to read or set the 47-bit smartclock timer. data is transferred to or from the smartclock timer when the rtc0set or rtc0cap bits are set. note: the lsb of capture0 is not used. the lsb of the 47-bit smartclock timer will appear in capture0.1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smartclock addresses: capture0: 0x00; capture1: 0x01; ca pture2: 0x02; capture3: 0x03; capture4: 0x04; capture5: 0x05 note: these registers are not sfrs. they can only be accessed indirectly through rtc0adr and rtc0dat.
rev. 0.8 187 C8051F410/1/2/3 internal register definition 20.7. alarmn: smartclock alarm 20.4. backup regulator and ram the smartclock includes a backup supply regulator that keeps the smartclock peripheral fully func - tional when v dd is turned off. the backup supply regulator regulates the v rtc-backup supply voltage, which can range from 1 v to 5.25 v. switchover logic automatically powers smartclock from the backup supply when the voltage at v rtc-backup is greater than v dd . the smartclock also includes 64 bytes of backup ram. this memory can be read and written indirectly using the ramaddr and ramdata internal registers. internal register definition 20.8. ramaddr: smartclock backup ram address bits 7?0: alarmn: smartclock alarm target. these 6 registers (alarm5?alarm0) are used to set an alarm event for the smartclock timer. the smartclock alarm should be disabled (rtc0aen=0) when updating these reg- isters. note: the lsb of alarm0 is not used. the lsb of the 47-bit smartclock timer will be compared against alarm0.1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smartclock addresses: alarm0: 0x08; alarm1: 0x09; alarm2: 0x0a; alarm3: 0x0b; alarm4: 0x0c; alarm5: 0x0d note: these registers are not sfrs. they can only be accessed indirectly through rtc0adr and rtc0dat. bit 7: ramaddr: smartclock battery backup ram address bits these bits select the smartclock backup ram byte that is targeted by ramdata. this address auto-increments after each read or write of ramdata. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smartclock address: note: this register is not an sfr. it can only be accessed indirectly through rtc0adr and rtc0dat. 0x0e
C8051F410/1/2/3 188 rev. 0.8 internal register definition 20.9. ramdata: smartclock backup ram data reads and writes of ramdata load the value at address ramaddr into rtc0dat. the following exam - ple writes 0xa5 to address 0x20 in the ram and reads the value back to a temporary variable: // in 'c': unsigned char temp = 0x00; // unlock the smartclock interface rtc0key = 0xa5; rtc0key = 0xf1; // enable the smartclock rtc0adr = 0x06; // address the rtc0cn register rtc0dat = 0x80; // enable the smartclock while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit // write to the smartclock ram rtc0adr = 0x0e; // address the ramaddr register rtc0dat = 0x20; // write the address of 0x20 to ramaddr while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit rtc0adr = 0x0f; // address the ramdata register rtc0dat = 0xa5; // write 0xa5 to ram address 0x20 while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit // read from the smartclock ram rtc0adr = 0x0e; // address the ramaddr register rtc0dat = 0x20; // write the address of 0x20 to ramaddr while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit rtc0adr = 0x0f; // address the ramdata register rtc0adr |= 0x80; // initiate a read of the ramdata register while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit temp = rtc0dat; // read the value of ram address 0x20 ; in assembly: ; unlock the smartclock interface mov rtc0key, #0a5h mov rtc0key, #0f1h bit 7: ramdata: smartclock battery backup ram data bits. these bits provide read and write access to the smartclock backup ram byte that is selected by ramaddr. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smartclock address: note: this register is not an sfr. it can only be accessed indirectly through rtc0adr and rtc0dat. 0x0f
rev. 0.8 189 C8051F410/1/2/3 ; enable the smartclock mov rtc0adr, #06h ; address the rtc0cn register mov rtc0dat, #080h ; enable the smartclock l0: mov a, rtc0adr ; poll on the busy bit jb acc.7, l0 ; write to the smartclock ram mov rtc0adr, #0eh ; address the ramaddr register mov rtc0dat, #20h ; write the address of 0x20 to ramaddr l1: mov a, rtc0adr ; poll on the busy bit jb acc.7, l1 mov rtc0adr, #0fh ; address the ramdata register mov rtc0dat, #0a5h ; write 0xa5 to ram address 0x20 l2: mov a, rtc0adr ; poll on the busy bit jb acc.7, l2 ; read from the smartclock ram mov rtc0adr, #0eh ; address the ramaddr register mov rtc0dat, #20h ; write the address of 0x20 to ramaddr l3: mov a, rtc0adr ; poll on the busy bit jb acc.7, l3 mov rtc0adr, #0fh ; address the ramdata register orl rtc0adr, #80h ; initiate a read of the ramdata register l4: mov a, rtc0adr ; poll on the busy bit jb acc.7, l4 movr0, #80h mov@r0, rtc0dat ; read the value of ram address 0x20 into ; the 128-byte internal ram to reduce the number of instructions necessary to read and write sections of the 64-byte ram, the ramaddr register automatically increments after each write or read. the following c example initializes the entire 64-byte ram to 0xa5 and copies this value from the ram to an array using the auto-increment feature: // in 'c': unsigned char ram_data[64] = 0x00; unsigned char addr; // unlock smartclock, enable smartclock // write to the entire smartclock ram rtc0adr = 0x0e; // address the ramaddr register rtc0dat = 0x00; // write the address of 0x00 to ramaddr while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit rtc0adr = 0x0f; // address the ramdata register for (addr = 0; addr < 64; addr++) { rtc0dat = 0xa5; // write 0xa5 to every ram address while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit } // read from the entire smartclock ram rtc0adr = 0x0e; // address the ramaddr register
C8051F410/1/2/3 190 rev. 0.8 rtc0dat = 0x00; // write the address of 0x00 to ramaddr while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit rtc0adr = 0x0f; // address the ramdata register for (addr = 0; addr < 64; addr++) { rtc0adr |= 0x80; // initiate a read of the ramdata register while ((rtc0adr & 0x80) == 0x80); // poll on the busy bit ram_data[addr] = rtc0dat; // copy the data from the entire ram }
rev. 0.8 191 C8051F410/1/2/3 21. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 2, and compatible with the i2c serial bus. reads and writes to the interface by the system controller are byte oriented with the smbus interface autonomously controlling the serial transfer of the data. data can be transferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and generation. three sfrs are associated with the smbus: smb0cf configures the smbus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. figure 21.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n
C8051F410/1/2/3 192 rev. 0.8 21.1. supporting documents it is assumed the reader is familiar with or has access to the following supporting documents: 1. the i2c manual (an10216-01), philips semiconductor. 2. system management bus specification -- version 2, sbs implementers forum. 21.2. smbus configuration figure 21.2 shows a typical smbus configuration. the smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. every device connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 21.2. typical smbus configuration note: it is recommended that the sda and scl pins be configured for high impedance overdrive mode. see section ?18. port input/output? on page 147 for more information. 21.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addressed slave transmitter to a master receiver (read). the master device initiates both types of data transfers and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. note that it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. v supply = 5 v master device slave device 1 slave device 2 v supply = 3 v v supply = 5 v v supply = 3 v sd a sc l
rev. 0.8 193 C8051F410/1/2/3 a typical smbus transaction consists of a start condition followed by an address byte (bits7-1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. each byte that is received (by a master or slave) must be acknowledged (ack) with a low sda during a high scl (see figure 21.3 ). if the receiving device does not ack, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmits the slave address and direction bit. if the trans - action is a write operation from the master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations, the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 21.3 illustrates a typical smbus transaction. figure 21.3. smbus transaction 21.3.1. arbitration a master may start a transfer only if the bus is free. the bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?21.3.4. scl high (smbus free) timeout? on page 194 ). in the event that two or more devices attempt to begin a transfer at the same time, an arbi - tration scheme is employed to force one master to give up the bus. the master devices continue transmit - ting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting the high will detect a low sda and lose the arbitration. the win - ning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destructive: one device always wins, and no data is lost. 21.3.2. clock low extension smbus provides a clock synchronization mechanism, similar to i2c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
C8051F410/1/2/3 194 rev. 0.8 21.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct the error condition. to solve this problem, the smbus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condition. devices that have detected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 21.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the smbfte bit in smb0cf is set, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master start, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation. enabling the bus free timeout is recom - mended. 21.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is determined by user software. the smbus interface provides the following application-independent features: byte-wise serial data transfers clock signal generation on scl (master mode only) and sda data synchronization timeout/bus error recognition, as defined by the smb0cf configuration register start/stop timing, detection, and generation bus arbitration interrupt generation status information smbus interrupts are generated for each data byte or slave address that is transferred. when transmitting, this interrupt is generated after the ack cycle so that software may read the received ack value; when receiving data, this interrupt is generated before the ack cycle so that software may define the outgoing ack value. see section ?21.5. smbus transfer modes? on page 201 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected). software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. the smb0cn register is described in section ?21.4.2. smb0cn control register? on page 198 ; table 21.4 provides a quick smb0cn decoding refer - ence.
rev. 0.8 195 C8051F410/1/2/3 smbus configuration options include: timeout detection (scl low timeout and/or bus free timeout) sda setup and hold time extensions slave event enable/disable clock source selection these options are selected in the smb0cf register, as described in section ?21.4.1. smbus configura - tion register? on page 195 . 21.4.1. smbus configuration register the smbus configuration register (smb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus interface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave interrupts. when the inh bit is set, all slave events will be inhibited following the next start (interrupts will continue for the duration of the current transfer). the smbcs1-0 bits select the smbus clock source, which is used only when operating as a master or when the bus free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 21.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?24. timers? on page 231 . equation 21.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 21.1 . when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 21.2 . equation 21.2. typical smbus bit rate table 21.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow --------------------------------------------- - == bitrate f clocksourceoverflow 3 --------------------------------------------- - =
C8051F410/1/2/3 196 rev. 0.8 figure 21.4 shows the typical scl generation described by equation 21.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exceed the limits defined by equation equation 21.1 . figure 21.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute minimum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 21.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. note: for scl operation above 100 khz, exthold should be cleared to ?0?. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?21.3.3. scl low timeout? on page 194 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service rou - tine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 21.4 ). when a free timeout is detected, the interface will respond as if a stop was detected (an interrupt will be generated, and sto will be set). enabling the bus free timeout is recommended. table 21.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low - 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks *note: setup time for ack bit transmissions and the msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. scl timer source overflows scl high timeout t low t high
rev. 0.8 197 C8051F410/1/2/3 sfr definition 21.1. smb0cf: smbus clock/configuration bit7: ensmb: smbus enable. this bit enables/disables the smbus interface. when enabled, the interface constantly mon- itors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit6: inh: smbus slave inhibit. when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit5: busy: smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. bit4: exthold: smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 21.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit3: smbtoe: smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. bit2: smbfte: smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. bits1?0: smbcs1?smbcs0: smbus clock source selection. these two bits select the smbus clock source, which is used to generate the smbus bit rate. the selected device should be configured according to equation 21.1. r/w r/w r r/w r/w r/w r/w r/w reset value ensmb inh busy exthold smbtoe smbfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1 smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
C8051F410/1/2/3 198 rev. 0.8 21.4.2. smb0cn control register smb0cn is used to control the interface and to provide status information (see sfr definition 21.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master and txmode indicate the master/slave state and transmit/receive modes, respectively. sta and sto indicate that a start and/or stop has been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a ?1? to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a ?1? to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if software does not write the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not acknowledged, further slave events will be ignored until the next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see table 21.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. ta b l e 21.3 lists all sources for hardware changes to the smb0cn bits. refer to table 21.4 for smbus sta - tus decoding using the smb0cn register.
rev. 0.8 199 C8051F410/1/2/3 sfr definition 21.2. smb0cn: smbus control bit7: master: smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit6: txmode: smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit5: sta: smbus start flag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a stop is received or a timeout is detected). if sta is set by software as an active master, a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit4: sto: smbus stop flag. if set by hardware, this bit must be cleared by software. write: 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop condition to be transmitted after the next ack cycle. when the stop condition is generated, hardware clears sto to logic 0. if both sta and sto are set, a stop condition is transmitted followed by a start condition. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit3: ackrq: smbus acknowledge request this read-only bit is set to logic 1 when the smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit2: arblost: smbus arbitration lost indicator. this read-only bit is set to logic 1 when the smbus loses arbitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit1: ack: smbus acknowledge flag. this bit defines the out-going ack level and records incoming ack levels. it should be writ- ten each time a byte is received (when ackrq=1), or read after each byte is transmitted. 0: a "not acknowledge" has been received (if in transmitter mode) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been received (if in transmitter mode) or will be transmitted (if in receiver mode). bit0: si: smbus interrupt flag. this bit is set by hardware under the conditions listed in table 21.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. r r r/w r/w r r r/w r/w reset value master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xc0
C8051F410/1/2/3 200 rev. 0.8 table 21.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master a start is generated. a stop is generated. arbitration is lost. txmode start is generated. smb0dat is written before the start of an smbus frame. a start is detected. arbitration is lost. smb0dat is not written before the start of an smbus frame. sta a start followed by an address byte is received. must be cleared by software. sto a stop is detected while addressed as a slave. arbitration is lost due to a detected stop. a pending stop is generated. if sto is set by hardware, it must be cleared by software. ackrq a byte has been received and an ack response value is needed. after each ack cycle. arblost a repeated start is detected as a master when sta is low (unwanted repeated start). scl is sensed low while attempting to gener - ate a stop or repeated start condition. sda is sensed low while transmitting a ?1? (excluding ack bits). each time si is cleared. ack the incoming ack value is low (acknowl - edge). the incoming ack value is high (not acknowledge). si a start has been generated. lost arbitration. a byte has been transmitted and an ack/nack received. a byte has been received. a start or repeated start followed by a slave address + r/w has been received. a stop has been received. must be cleared by software.
rev. 0.8 201 C8051F410/1/2/3 21.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted out msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. sfr definition 21.3. smb0dat: smbus data 21.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mode any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the interrupt is generated before the ack cycle when operat - ing as a receiver, and after the ack cycle when operating as a transmitter. 21.5.1. master transmitter mode serial data is transmitted on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 0 (write). the master then transmits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written following a master transmitter interrupt. figure 21.5 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur after the ack cycle in this mode. bits7?0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial inter- face or a byte that has just been received on the smbus serial interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2
C8051F410/1/2/3 202 rev. 0.8 figure 21.5. typical mast er transmitter sequence 21.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direc - tion bit. in this case the data direction bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to ?1? and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the outgoing acknowledge value (note: writing a ?1? to the ack bit gen - erates an ack; writing a ?0? generates a nack). software should write a ?0? to the ack bit after the last byte is received, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. note that the interface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 21.6 shows a typical master receiver sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. figure 21.6. typical master receiver sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
rev. 0.8 203 C8051F410/1/2/3 21.5.3. slave receiver mode serial data is received on sda and the clock is received on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0dat is written while an active slave receiver. figure 21.7 shows a typical slave receiver sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. figure 21.7. typical slave receiver sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
C8051F410/1/2/3 204 rev. 0.8 21.5.4. slave transmitter mode serial data is transmitted on sda and the clock is received on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave transmitter mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhibited until a start is detected. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and trans - mits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be gener - ated if smb0dat is written following a received nack while in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 21.8 shows a typical slave transmitter sequence. two transmitted data bytes are shown, though any number of bytes may be trans - mitted. notice that the ?data byte transferred? interrupts occur after the ack cycle in this mode. figure 21.8. typical slav e transmitter sequence 21.6. smbus status decoding the current smbus status can be easily decoded using the smb0cn register. in the table below, status vector refers to the four upper bits of smb0cn: master, txmode, sta, and sto. note that the shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the smbus specification. highlighted responses are allowed but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
rev. 0.8 205 C8051F410/1/2/3 table 21.4. smbus status decoding mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x abort transfer. 0 1 x 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 0 0 x end transfer with stop. 0 1 x end transfer with stop and start another transfer. 1 1 x send repeated start. 1 0 x switch to master receiver mode (clear si without writ - ing new data to smb0dat). 0 0 x master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 send nack to indicate last byte, and send stop. 0 1 0 send nack to indicate last byte, and send stop fol - lowed by start. 1 1 0 send ack followed by repeated start. 1 0 1 send nack to indicate last byte, and send repeated start. 1 0 0 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0
C8051F410/1/2/3 206 rev. 0.8 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expect - ing stop condition). 0 0 x 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 01x a slave byte was transmitted; error detected. no action required (expect - ing master to end transfer). 0 0 x 0101 0 x x an illegal stop or bus error was detected while a slave transmis - sion was in progress. clear sto. 0 0 x slave receiver 0010 10x a slave address was received; ack requested. acknowledge received address. 0 0 1 do not acknowledge received address. 0 0 0 11x lost arbitration as master; slave address received; ack requested. acknowledge received address. 0 0 1 do not acknowledge received address. 0 0 0 reschedule failed transfer; do not acknowledge received address. 1 0 0 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 0001 11x lost arbitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 00x a stop was detected while addressed as a slave transmitter or slave receiver. clear sto. 0 0 x 01x lost arbitration due to a detected stop. abort transfer. 0 0 x reschedule failed transfer. 1 0 x 0000 10x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 do not acknowledge received byte. 0 0 0 11x lost arbitration while transmitting a data byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 table 21.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
rev. 0.8 207 C8051F410/1/2/3 22. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?22.1. enhanced baud rate generation? on page 208 ). received data buffering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous data byte. uart0 has two associated sfrs: serial control register 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 22.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch)
C8051F410/1/2/3 208 rev. 0.8 22.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 22.2 ), which is not user- accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 22.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?24.1.3. mode 2: 8-bit counter/timer with auto-reload? on page 233 ). the timer 1 reload value should be set so that over - flows will occur at two times the desired uart baud rate frequency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an external input t1. the uart0 baud rate is determined by equation 22.1 -a and equation 22.1 -b. equation 22.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (8-bit auto-reload mode reload value). timer 1 clock frequency is selected as described in section ?24. timers? on page 231 . a quick reference for typical baud rates and system clock frequencies is given in ta b l e 22.1 through ta b le 22.6 . note that the internal oscillator may still generate the system clock when the external oscillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate = t1_overflow_rate t1 clk 256 th1 ? ------------------------- - = a) b)
rev. 0.8 209 C8051F410/1/2/3 22.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. figure 22.3. uart interconnect diagram 22.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin and received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins when software writes a data byte to the sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmission (the beginning of the stop-bit time). data recep - tion can begin any time after the ren0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when either ti0 or ri0 is set. figure 22.4. 8-bit uart timing diagram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
C8051F410/1/2/3 210 rev. 0.8 22.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the ninth transmit data bit is determined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enable bit (scon0.4) is set to ?1?. after the stop bit is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these conditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a uart0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. figure 22.5. 9-bit uart timing diagram 22.3. multiproces sor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor configures its uart such that when a stop bit is received, the uart will generate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. if the addresses match, the slave will clear its mce0 bit to enable interrupts on the reception of the following data byte(s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
rev. 0.8 211 C8051F410/1/2/3 figure 22.6. uart mult i-processor mode in terconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
C8051F410/1/2/3 212 rev. 0.8 sfr definition 22.1. scon0: serial port 0 control bit7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. bit6: unused. read = 1b. write = don?t care. bit5: mce0: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. s0mode = 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. s0mode = 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic 1. bit4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. bit0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enabled, setting this bit to ?1? causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by soft- ware. r/w r r/w r/w r/w r/w r/w r/w reset value s0mode - mce0 ren0 tb80 rb80 ti0 ri0 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x98
rev. 0.8 213 C8051F410/1/2/3 sfr definition 22.2. sbuf0: serial (uart0) port data buffer bits7?0: sbuf0[7:0]: serial data buffer bits 7-0 (msb-lsb) this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmis- sion. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the con- tents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99
C8051F410/1/2/3 214 rev. 0.8 table 22.1. timer settings for standard baud rates using the internal oscillator frequency: 24.5 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk from internal osc. 230400 -0.32% 106 sysclk xx 1 0xcb 115200 -0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 -0.32% 848 sysclk / 4 01 0 0x96 14400 0.15% 1704 sysclk / 12 00 0 0xb9 9600 -0.32% 2544 sysclk / 12 00 0 0x96 2400 -0.32% 10176 sysclk / 48 10 0 0x96 1200 0.15% 20448 sysclk / 48 10 0 0x2b x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 24.1 . table 22.2. timer settings for standard baud rates using an external 25.0 mhz oscillator frequency: 25.0 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk from external osc. 230400 -0.47% 108 sysclk xx 1 0xca 115200 0.45% 218 sysclk xx 1 0x93 57600 -0.01% 434 sysclk xx 1 0x27 28800 0.45% 872 sysclk / 4 01 0 0x93 14400 -0.01% 1736 sysclk / 4 01 0 0x27 9600 0.15% 2608 extclk / 8 11 0 0x5d 2400 0.45% 10464 sysclk / 48 10 0 0x93 1200 -0.01% 20832 sysclk / 48 10 0 0x27 sysclk from internal osc. 57600 -0.47% 432 extclk / 8 11 0 0xe5 28800 -0.47% 864 extclk / 8 11 0 0xca 14400 0.45% 1744 extclk / 8 11 0 0x93 9600 0.15% 2608 extclk / 8 11 0 0x5d x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 24.1 .
rev. 0.8 215 C8051F410/1/2/3 table 22.3. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 1 0xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysclk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 24.1 . table 22.4. timer settings for standard baud rates using an external 18.432 mhz oscillator frequency: 18.432 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 80 sysclk xx 1 0xd8 115200 0.00% 160 sysclk xx 1 0xb0 57600 0.00% 320 sysclk xx 1 0x60 28800 0.00% 640 sysclk / 4 01 0 0xb0 14400 0.00% 1280 sysclk / 4 01 0 0x60 9600 0.00% 1920 sysclk / 12 00 0 0xb0 2400 0.00% 7680 sysclk / 48 10 0 0xb0 1200 0.00% 15360 sysclk / 48 10 0 0x60 sysclk from internal osc. 230400 0.00% 80 extclk / 8 11 0 0xfb 115200 0.00% 160 extclk / 8 11 0 0xf6 57600 0.00% 320 extclk / 8 11 0 0xec 28800 0.00% 640 extclk / 8 11 0 0xd8 14400 0.00% 1280 extclk / 8 11 0 0xb0 9600 0.00% 1920 extclk / 8 11 0 0x88 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 24.1 .
C8051F410/1/2/3 216 rev. 0.8 table 22.5. timer settings for standard baud rates using an external 11.0592 mhz oscillator frequency: 11.0592 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 48 sysclk xx 1 0xe8 115200 0.00% 96 sysclk xx 1 0xd0 57600 0.00% 192 sysclk xx 1 0xa0 28800 0.00% 384 sysclk xx 1 0x40 14400 0.00% 768 sysclk / 12 00 0 0xe0 9600 0.00% 1152 sysclk / 12 00 0 0xd0 2400 0.00% 4608 sysclk / 12 00 0 0x40 1200 0.00% 9216 sysclk / 48 10 0 0xa0 sysclk from internal osc. 230400 0.00% 48 extclk / 8 11 0 0xfd 115200 0.00% 96 extclk / 8 11 0 0xfa 57600 0.00% 192 extclk / 8 11 0 0xf4 28800 0.00% 384 extclk / 8 11 0 0xe8 14400 0.00% 768 extclk / 8 11 0 0xd0 9600 0.00% 1152 extclk / 8 11 0 0xb8 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 24.1 . table 22.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator frequency: 3.6864 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 16 sysclk xx 1 0xf8 115200 0.00% 32 sysclk xx 1 0xf0 57600 0.00% 64 sysclk xx 1 0xe0 28800 0.00% 128 sysclk xx 1 0xc0 14400 0.00% 256 sysclk xx 1 0x80 9600 0.00% 384 sysclk xx 1 0x40 2400 0.00% 1536 sysclk / 12 00 0 0xc0 1200 0.00% 3072 sysclk / 12 00 0 0x80 sysclk from internal osc. 230400 0.00% 16 extclk / 8 11 0 0xff 115200 0.00% 32 extclk / 8 11 0 0xfe 57600 0.00% 64 extclk / 8 11 0 0xfc 28800 0.00% 128 extclk / 8 11 0 0xf8 14400 0.00% 256 extclk / 8 11 0 0xf0 9600 0.00% 384 extclk / 8 11 0 0xe8 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 24.1 .
rev. 0.8 217 C8051F410/1/2/3 23. enhanced serial peripheral interface (spi0) the serial peripheral interface (spi0) provides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas - ters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding conten - tion on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional general pur - pose port i/o pins can be used to select multiple slave devices in master mode. figure 23.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien
C8051F410/1/2/3 218 rev. 0.8 23.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 23.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output from a master device and an input to slave devices. it is used to serially transfer data from the master to the slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 23.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance state when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not selected. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 23.1.3. serial clock (sck) the serial clock (sck) signal is an output from the master device and an input to slave devices. it is used to synchronize the transfer of data between the master and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 23.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possible modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disables the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 operates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determines what logic level the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 23.2, figure 23.3, and figure 23.4 for typical connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ? 18. port input/output ? on page 147 for general purpose port i/o and crossbar information.
rev. 0.8 219 C8051F410/1/2/3 23.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while providing the serial clock on sck. the spif (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabled, an interrupt request is generated when the spif flag is set. while the spi0 master transfers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers data to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-first into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another master is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generated (modf, spi0cn.5 = 1). mode fault will generate an interrupt if enabled. spi0 must be manually re-enabled in software under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individually (if needed) using general-purpose i/o pins. figure 23.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. in this mode, nss is not used and is not mapped to an external port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 23.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin and can be used as a slave-select signal for a single spi device. in this mode, the output value of nss is controlled (in software) with the bit nssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 23.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
C8051F410/1/2/3 220 rev. 0.8 figure 23.2. multiple-master mode connection diagram figure 23.3. 3-wire single master and slave mode connection diagram figure 23.4. 4-wire single master and slave mode connection diagram 23.3. spi0 slave mode operation when spi0 is enabled and not configured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin and out through the miso pin by a master device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted into the shift register, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double-buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the shift register already contains data, the spi will load the shift register with the transmit buffer?s contents after the last sck edge of the next (or current) spi transfer. master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss
rev. 0.8 221 C8051F410/1/2/3 the shift register contents are locked after the slave detects the first edge of sck. writes to spi0dat that occur after the first sck edge will be held in the tx latch until the end of the current transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of nss. note that the nss sig - nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 23.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is not a way of uniquely addressing the device in 3-wire slave mode, spi0 must be the only slave device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. the bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 23.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 23.4. spi0 inte rrupt sources when spi0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: note that all of the following interrupt bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmit buffer will not be written.this flag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master in multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 and allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is set to logic 1 when configured as a slave, and a transfer is completed while the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 23.5. serial clock timing four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit (spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between a rising edge or a falling edge. both master and slave devices must be configured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships are shown in figure 23.5 . the spi0 clock rate register (spi0ckr) as shown in sfr definition 23.3 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz,
C8051F410/1/2/3 222 rev. 0.8 whichever is slower. when the spi is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchronously with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issues sck, nss, and the serial input data synchronously with the slave?s system clock. figure 23.5. data/clock timing relationship 23.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi
rev. 0.8 223 C8051F410/1/2/3 sfr definition 23.1. spi0cfg: spi0 configuration bit 7: spibsy: spi busy (read only). this bit is set to logic 1 when a spi transfer is in progress (master or slave mode). bit 6: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. bit 5: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data centered on first edge of sck period.* 1: data centered on second edge of sck period.* bit 4: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bit 3: slvsel: slave selected flag (read only). this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but rather a de-glitched version of the pin input. bit 2: nssin: nss instantaneous pin input (read only). this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. bit 1: srmt: shift register empty (valid in slave mode, read only). this bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. note: srmt = 1 when in master mode. bit 0: rxbmt: receive buffer empty (valid in slave mode, read only). this bit will be set to logic 1 when the receive buffer has been read and contains no new information. if there is new information available in the receive buffer that has not been read, this bit will return to logic 0. note: rxbmt = 1 when in master mode. *note: see table 23.1 for timing parameters. r r/w r/w r/w r r r r reset value spibsy msten ckpha ckpol slvsel nssin srmt rxbmt 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa1
C8051F410/1/2/3 224 rev. 0.8 sfr definition 23.2. spi0cn: spi0 control bit 7: spif: spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit 6: wcol: write collision flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a data transfer was in progress. this bit is not automatically cleared by hardware. it must be cleared by software. bit 5: modf: mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). this bit is not auto- matically cleared by hardware. it must be cleared by software. bit 4: rxovrn: receive overrun flag (slave mode only). this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. this bit is not automatically cleared by hardware. it must be cleared by software. bits 3?2: nssmd1?nssmd0: slave select mode. selects between the following nss operation modes: (see section ?23.2. spi0 master mode operation? on page 219 and section ?23.3. spi0 slave mode operation? on page 220 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (default). nss is always an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an output from the device and will assume the value of nssmd0. bit 1: txbmt: transmit buffer empty. this bit will be set to logic 0 when new data has been written to the transmit buffer. when data in the transmit buffer is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. bit 0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. 1: spi enabled. r/w r/w r/w r/w r/w r/w r r/w reset value spif wcol modf rxovrn nssmd1 nssmd0 txbmt spien 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xf8
rev. 0.8 225 C8051F410/1/2/3 sfr definition 23.3. spi0ckr: spi0 clock rate bits 7?0: scr7?scr0: spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa2 f sck 2000000 241 + () -------------------------- = f sck 200 khz = f sck sysclk 2 spi 0 ckr 1 + () ------------------------------------------------ - =
C8051F410/1/2/3 226 rev. 0.8 sfr definition 23.4. spi0dat: spi0 data bits 7?0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmit buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa3
rev. 0.8 227 C8051F410/1/2/3 figure 23.6. spi master timing (ckpha = 0) figure 23.7. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
C8051F410/1/2/3 228 rev. 0.8 figure 23.8. spi slave timing (ckpha = 0) figure 23.9. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz
rev. 0.8 229 C8051F410/1/2/3 table 23.1. spi slave timing parameters parameter description min max units master mode timing* (see figure 23.6 and figure 23.7) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck sample edge 20 ? ns t mih sck sample edge to miso change 0 ? ns slave mode timing* (see figure 23.8 and figure 23.9) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk) in ns.
C8051F410/1/2/3 230 rev. 0.8 n otes :
rev. 0.8 231 C8051F410/1/2/3 24. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with other device peripherals or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of oper - ation. timer 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. timer 2 and timer 3 also have a smartclock capture mode that can be used to measure the smartclock clock with respect to another oscillator. timers 0 and 1 may be clocked by one of five sources, determined by the timer mode select bits (t1m- t0m) and the clock scale bits (sca1-sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 24.3 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock's frequency can be counted. the input signal need not be peri - odic, but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. 24.1. timer 0 and timer 1 each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie register ( section ?12.4. interrupt register descriptions? on page 112 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( section 12.4 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1-t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 24.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit counter/timer. tl0 holds the five lsbs in bit positions tl0.4-tl0.0. the three upper bits of tl0 (tl0.7-tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled. timer 0 and timer 1 modes: timer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
C8051F410/1/2/3 232 rev. 0.8 the c/t0 bit (tmod.2) selects the counter/timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?18.1. priority crossbar decoder? on page 149 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 24.3 ). setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or the input signal /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 12.7. ?it01cf: int0/int1 configuration? on page 118 ). setting gate0 to ?1? allows the timer to be controlled by the external input signal /int0 (see section ?12.4. interrupt register descriptions? on page 112 ), facilitating pulse width measurements. setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1; the /int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 12.7. ?it01cf: int0/int1 configuration? on page 118 ). figure 24.1. t0 mode 0 block diagram tr0 gate0 /int0 counter/timer 0xxdisabled 1 0 x enabled 1 1 0 disabled 111enabled x = don't care it01cf
rev. 0.8 233 C8051F410/1/2/3 24.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the counter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 24.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload value. when the counter in tl0 overflows from all ones to 0x00, the timer overflow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interrupt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal /int0 is active as defined by bit in0pl in register it01cf (see section ?12.5. external interrupts? on page 117 for details on the external input signals /int0 and /int1). figure 24.2. t0 mode 2 block diagram it01cf
C8051F410/1/2/3 234 rev. 0.8 24.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and uart. while timer 0 is oper - ating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 24.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 0.8 235 C8051F410/1/2/3 sfr definition 24.1. tcon: timer control bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. when it1 = 0, this flag is set to ?1? when /int1 is active as defined by bit in1pl in register it01cf (see sfr definition 12.7. ?it01cf: int0/int1 con- figuration? on page 118). bit2: it1: interrupt 1 type select. this bit selects whether the configured /int1 interrupt will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 12.7. ?it01cf: int0/int1 configuration? on page 118). 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. when it0 = 0, this flag is set to ?1? when /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 12.7. ?it01cf: int0/int1 con- figuration? on page 118). bit0: it0: interrupt 0 type select. this bit selects whether the configured /int0 interrupt will be edge or level sensitive. /int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 12.7. ?it01cf: int0/int1 configuration? on page 118). 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x88
C8051F410/1/2/3 236 rev. 0.8 sfr definition 24.2. tmod: timer mode bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in regis- ter it01cf (see sfr definition 12.7. ?it01cf: int0/int1 configuration? on page 118). bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5?4: t1m1?t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in regis- ter it01cf (see sfr definition 12.7. ?it01cf: int0/int1 configuration? on page 118). bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1?0: t0m1?t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: two 8-bit counter/timers
rev. 0.8 237 C8051F410/1/2/3 sfr definition 24.3. ckcon: clock control bit7: t3mh: timer 3 high byte clock select. this bit selects the clock supplied to the timer 3 high byte if timer 3 is configured in split 8- bit timer mode. t3mh is ignored if timer 3 is in any other mode. 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. bit6: t3ml: timer 3 low byte clock select. this bit selects the clock supplied to timer 3. if timer 3 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. bit5: t2mh: timer 2 high byte clock select. this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8- bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit4: t2ml: timer 2 low byte clock select. this bit selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit3: t1m: timer 1 clock select. this select the clock source supplied to timer 1. t1m is ignored when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 1 uses the system clock. bit2: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1-sca0. 1: counter/timer 0 uses the system clock. bits1?0: sca1?sca0: timer 0/1 prescale bits. these bits control the division of the clock supplied to timer 0 and timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value t3mh t3ml t2mh t2ml t1m t0m sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 note: external clock divided by 8 is synchronized with the system clock.
C8051F410/1/2/3 238 rev. 0.8 sfr definition 24.4. tl0: timer 0 low byte sfr definition 24.5. tl1: timer 1 low byte sfr definition 24.6. th0: timer 0 high byte sfr definition 24.7. th1: timer 1 high byte bits 7?0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a bits 7?0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8b bits 7?0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8c bits 7?0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8d
rev. 0.8 239 C8051F410/1/2/3 24.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 can also be used in capture mode to measure the smartclock clock frequency or the external oscillator clock frequency. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external oscillator source divided by 8 is synchronized with the system clock. 24.2.1. 16-bit timer with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 24.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally, if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn.5), an interrupt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 24.4. timer 2 16-b it mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len tmr2l overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
C8051F410/1/2/3 240 rev. 0.8 24.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bit timers (tmr2h and tmr2l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 24.5 . tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external clock select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 24.5. timer 2 8-bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrup t tmr2cn t2split tf2len tf2l tf2h t2xclk tr2 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 0.8 241 C8051F410/1/2/3 24.2.3. external/smartclock capture mode capture mode allows either the external oscillator or the smartclock clock to be measured against the system clock. the external oscillator and smartclock clock can also be compared against each other. timer 2 can be clocked from the system clock, the system clock divided by 12, the external oscillator divided by 8, or the smartclock clock divided by 8, depending on the t2ml (ckcon.4), t2xclk, and t2rclk settings. the timer will capture either every 8 external clock cycles or every 8 smartclock clock cycles, depending on the t2rclk setting. when a capture event is generated, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers (tmr2rlh:tmr2rll) and the tf2h flag is set. by recording the difference between two successive timer capture values, the external oscillator or smartclock clock can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the capture clock to achieve an accurate reading. timer 2 should be in 16-bit auto-reload mode when using capture mode. for example, if t2ml = 1b, t2rclk = 0b, and tf2cen = 1b, timer 2 will clock every sysclk and cap - ture every smartclock clock divided by 8. if the sysclk is 24.5 mhz and the difference between two successive captures is 5984, then the smartclock clock is: 24.5 mhz / (5984 / 8) = 0.032754 mhz or 32.754 khz. this mode allows software to determine the exact smartclock frequency in self-oscillate mode and the external oscillator frequency when an rc network or capacitor is used to generate the signal. figure 24.6. timer 2 capt ure mode block diagram tclk 0 1 tr2 tmr2h tmr2rlh tf2cen tmr2l tmr2rll interrupt tmr2cn tr2clk tf2cen tf2len tf2l tf2h t2xclk tr2 smartclock / 8 external osc. / 8 0 1 t2rclk 0 1 t2xclk sysclk smartclock / 8 external osc. / 8 0 1 t2rclk sysclk / 12 capture ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
C8051F410/1/2/3 242 rev. 0.8 sfr definition 24.8. tmr2cn: timer 2 control bit7: tf2h: timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automatically cleared by hardware and must be cleared by software. bit6: tf2l: timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf2len is set and timer 2 interrupts are enabled. tf2l will set when the low byte overflows regardless of the timer 2 mode. this bit is not automat- ically cleared by hardware. bit5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte interrupts. if tf2len is set and timer 2 inter- rupts are enabled, an interrupt will be generated when the low byte of timer 2 overflows. this bit should be cleared when operating timer 2 in 16-bit mode. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit4: tf2cen. timer 2 capture enable. 0: timer 2 capture mode disabled. 1: timer 2 capture mode enabled. bit3: t2split: timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit1: t2rclk: timer 2 capture mode. this bit controls the timer 2 capture source when tf2cen=1. if t2xclk = 1 and t2ml (ckcon.4) = 0, this bit also controls the clock source for timer 2. 0: capture every smartclock clock/8. if t2xclk = 1 and t2ml (ckcon.4) = 0, count at external oscillator/8. 1: capture every external oscillator/8. if t2xclk = 1 and t2ml (ckcon.4) = 0, count at smartclock clock/8. bit0: t2xclk: timer 2 external clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock uses the clock defined by the t2rclk bit. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf2h tf2l tf2len tf2cen t2split tr2 t2rclk t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xc8
rev. 0.8 243 C8051F410/1/2/3 sfr definition 24.9. tmr2rll: timer 2 reload register low byte sfr definition 24.10. tmr2rlh: timer 2 reload register high byte sfr definition 24.11. tmr2l: timer 2 low byte sfr definition 24.12. tmr2h timer 2 high byte bits 7?0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca bits 7?0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb bits 7?0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc bits 7?0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcd
C8051F410/1/2/3 244 rev. 0.8 24.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 can also be used in capture mode to measure the smartclock clock frequency or the external oscillator clock frequency. timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. 24.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tm3rll) is loaded into the timer 3 register as shown in figure 24.7 , and the timer 3 high byte overflow flag (tmr3cn.7) is set. if timer 3 interrupts are enabled, an interrupt will be generated on each timer 3 overflow. additionally, if timer 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 24.7. timer 3 16-b it mode block diagram external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 0.8 245 C8051F410/1/2/3 24.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bit timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 24.8 . tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external clock select bit (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3len is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 24.8. timer 3 8-bit mode block diagram t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrup t tmr3cn t3split tf3cen tf3len tf3l tf3h t3xclk tr3 to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
C8051F410/1/2/3 246 rev. 0.8 24.3.3. external/smartclock capture mode capture mode allows either the external oscillator or the smartclock clock to be measured against the system clock. the external oscillator and smartclock clock can also be compared against each other. timer 3 can be clocked from the system clock, the system clock divided by 12, the external oscillator divided by 8, or the smartclock clock divided by 8, depending on the t3ml (ckcon.6), t3xclk, and t3rclk settings. the timer will capture either every 8 external clock cycles or every 8 smartclock clock cycles, depending on the t3rclk setting. when a capture event is generated, the contents of timer 3 (tmr3h:tmr3l) are loaded into the timer 3 reload registers (tmr3rlh:tmr3rll) and the tf3h flag is set. by recording the difference between two successive timer capture values, the external oscillator or smartclock clock can be determined with respect to the timer 3 clock. the timer 3 clock should be much faster than the capture clock to achieve an accurate reading. timer 3 should be in 16-bit auto-reload mode when using capture mode. for example, if t3ml = 1b, t3rclk = 0b, and tf3cen = 1b, timer 3 will clock every sysclk and cap - ture every smartclock clock divided by 8. if the sysclk is 24.5 mhz and the difference between two successive captures is 5984, then the smartclock clock is: 24.5 mhz / (5984 / 8) = 0.032754 mhz or 32.754 khz. this mode allows software to determine the exact smartclock frequency in self-oscillate mode and the external oscillator frequency when an rc network or capacitor is used to generate the signal. figure 24.9. timer 3 capt ure mode block diagram tclk 0 1 tr3 tmr3h tmr3rlh tf3cen tmr3l tmr3rll interrupt tmr3cn tr3clk tf3cen tf3len tf3l tf3h t3xclk tr3 smartclock / 8 external osc. / 8 0 1 t3rclk 0 1 t3xclk sysclk smartclock / 8 external osc. / 8 0 1 t3rclk sysclk / 12 capture ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 0.8 247 C8051F410/1/2/3 sfr definition 24.13. tmr3cn: timer 3 control bit7: tf3h: timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0xffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. tf3h is not automatically cleared by hardware and must be cleared by software. bit6: tf3l: timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf3len is set and timer 3 interrupts are enabled. tf3l will set when the low byte overflows regardless of the timer 3 mode. this bit is not automat- ically cleared by hardware. bit5: tf3len: timer 3 low byte interrupt enable. this bit enables/disables timer 3 low byte interrupts. if tf3len is set and timer 3 inter- rupts are enabled, an interrupt will be generated when the low byte of timer 3 overflows. this bit should be cleared when operating timer 3 in 16-bit mode. 0: timer 3 low byte interrupts disabled. 1: timer 3 low byte interrupts enabled. bit4: tf3cen: timer 3 capture enable. 0: timer 3 capture mode disabled. 1: timer 3 capture mode enabled. bit3: t3split: timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. bit2: tr3: timer 3 run control. this bit enables/disables timer 3. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabled in this mode. 0: timer 3 disabled. 1: timer 3 enabled. bit1: t3rclk: timer 3 capture mode. this bit controls the timer 3 capture source when tf3cen=1. if t3xclk = 1 and t3ml (ckcon.6) = 0, this bit also controls the clock source for timer 3. 0: capture every smartclock clock/8. if t3xclk = 1 and t3ml (ckcon.6) = 0, count at external oscillator/8. 1: capture every external oscillator/8. if t3xclk = 1 and t3ml (ckcon.6) = 0, count at smartclock clock/8. bit0: t3xclk: timer 3 external clock select. this bit selects the external clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 external clock selection is the system clock divided by 12. 1: timer 3 external clock uses the clock defined by the t3rclk bit. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf3h tf3l tf3len tf3cen t3split tr3 t3rclk t3xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x91
C8051F410/1/2/3 248 rev. 0.8 sfr definition 24.14. tmr3rll: timer 3 reload register low byte sfr definition 24.15. tmr3rlh: timer 3 reload register high byte sfr definition 24.16. tmr3l: timer 3 low byte sfr definition 24.17. tmr3h timer 3 high byte bits 7-0: tmr3rll: timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x92 bits 7-0: tmr3rlh: timer 3 reload register high byte. the tmr3rlh holds the high byte of the reload value for timer 3. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x93 bits 7-0: tmr3l: timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x94 bits 7-0: tmr3h: timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x95
rev. 0.8 249 C8051F410/1/2/3 25. programmable counter array (pca0) the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. the pca consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?18.1. priority crossbar decoder? on page 149 for details on configuring the crossbar). the counter/timer is driven by a programmable timebase that can select between seven sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, smartclock clock divided by 8, timer 0 overflow, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, soft - ware timer, high-speed output, frequency output, 8-bit pwm, or 16-bit pwm (each mode is described in section ?25.2. capture/compare modules? on page 251 ). the pca is configured and controlled through the system controller's special function registers. the pca block diagram is shown in figure 25.1 important note: the pca module 5 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 25.3 for details. figure 25.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 cex1 eci crossbar cex2 cex3 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 smartclock/8 capture/compare module 4 cex4 capture/compare module 5 cex5
C8051F410/1/2/3 250 rev. 0.8 25.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bit sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accurate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 25.1 . when the counter/timer overflows from 0xffff to 0x0000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft - ware (note: pca0 interrupts must be globally enabled bef ore cf interrupts are recognized. pca0 interrupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register allows the pca to cont inue normal operation while the cpu is in idle mode. figure 25.2. pca counter/timer block diagram table 25.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator source divided by 8* 1 1 0 smartclock clock divided by 8* *note: external clock divided by 8 and smartclock clock divided by 8 are synchronized with the system clock. pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 rtc0 clock/8 110 pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3
rev. 0.8 251 C8051F410/1/2/3 25.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special function registers (sfrs) associated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 25.2 summarizes the bit settings in the pca0cpmn registers used to select the pca capture/com - pare module?s operating modes. setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec - ognized. pca0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. see figure 25.3 for details on the pca interrupt configuration. figure 25.3. pca interrupt block diagram table 25.2. pca0cpm register settings fo r pca capture/compare modules pwm16 ecom capp capn mat tog pwm eccf operation mode x x 10000x capture triggered by positive edge on cexn x x 01000x capture triggered by negative edge on cexn x x 11000x capture triggered by transition on cexn x 1 00100xsoftware timer x 1 00110xhigh s peed output x 1 0 0 x 1 1 x frequency output 0 1 0 0 x 0 1 x 8-bit pulse width modulator 1 1 0 0 x 0 1 x 16-bit pulse width modulator x = don?t care pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l e c f c p s 1 c p s 0 c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 0 1 pca module 3 (ccf3) eccf3 eccf4 pca counter/ t imer overflow 0 1 interrup t priority decode r epca0 (eie1.4) pca0cpmn (for n = 0 to 5) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 1 pca module 4 (ccf4) 0 1 pca module 5 (ccf5) 0 1 ea (ie.7) 0 1 eccf5
C8051F410/1/2/3 252 rev. 0.8 25.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin causes the pca to capture the value of the pca counter/timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. if both cappn and capnn bits are set to logic 1, then the state of the port pin associated with cexn can be read directly to determine whether a rising-edge or falling-edge caused the capture. figure 25.4. pca capt ure mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca interrupt pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3
rev. 0.8 253 C8051F410/1/2/3 25.2.2. software timer (compare) mode in software timer mode, the pca counter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. figure 25.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 pca interrupt 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3
C8051F410/1/2/3 254 rev. 0.8 25.2.3. high speed output mode in high speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16-bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high- speed output mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. figure 25.6. pca high-speed output mode diagram note: the initial state of the toggle output is logic 1 and is initialized to this state when the module enters high speed output mode. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln pca interrupt 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3
rev. 0.8 255 C8051F410/1/2/3 25.2.4. frequency output mode frequency output mode produces a programmable-frequency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 25.1 . equation 25.1. square wave fr equency output where f pca is the frequency of the clock selected by the cps2-0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the high byte is added to the matched value in pca0cpln. fre - quency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn register. figure 25.7. pca fre quency output mode f cexn f pca 2 pca 0 cphn ---------------------------------------- - = n ote: a value of 0x00 in the pca0cphn register is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase 000 0 match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 1
C8051F410/1/2/3 256 rev. 0.8 25.2.5. 8-bit pulse width modulator mode each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is dependent on the timebase for the pca counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cphn capture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be set. when the count value in pca0l overflows, the cexn output will be reset (see figure 25.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 25.2 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. equation 25.2. 8-bit pwm duty cycle using equation 25.2, the largest duty cycle is 100% (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. figure 25.8. pca 8-bit pwm mode diagram dutycycle 256 pca 0 cphn ? () 256 --------------------------------------------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 0000 0 q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0
rev. 0.8 257 C8051F410/1/2/3 25.2.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare mod - ule defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the output on cexn is asserted high; when the counter overflows, cexn is asserted low. to output a varying duty cycle, new value writes should be synchronized with pca ccfn match inter - rupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compare register writes. the duty cycle for 16-bit pwm mode is given by equation 25.3 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. equation 25.3. 16-bit pwm duty cycle using equation 25.3, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. figure 25.9. pca 16-bit pwm mode 25.3. watchdog timer mode a programmable watchdog timer (wdt) function is available through the pca module 5. the wdt is used to generate a reset if the time between writes to the wdt update register (pca0cph5) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, module 5 operates as a watchdog timer (wdt). the module 5 high byte is compared to the pca counter high byte; the module 5 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. dutycycle 65536 pca 0 cpn ? () 65536 ---------------------------------------------------- - = pca0cpln pca0cphn enable pca timebase 0000 0 pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l
C8051F410/1/2/3 258 rev. 0.8 25.3.1. watchdog timer operation while the wdt is enabled: pca counter is forced on. writes to pca0l and pca0h are not allowed. pca clock source bits (cps2-cps0) are frozen. pca idle control bit (cidl) is frozen. module 5 is forced into software timer mode. writes to the module 5 mode register (pca0cpm5) are disabled. while the wdt is enabled, writes to the cr bit will not change the pca counter state; the counter will run until the wdt is disabled. the pca counter run control (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a match occurs between pca0cph5 and pca0h while the wdt is enabled, a reset will be generated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph5. upon a pca0cph5 write, pca0h plus the offset held in pca0cpl5 is loaded into pca0cph5 (see figure 25.10 ). figure 25.10. pca module 5 with watchdog timer enabled pca0h enable pca0l overflow rese t pca0cpl5 8-bit adder pca0cph5 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph5 8-bit comparator
rev. 0.8 259 C8051F410/1/2/3 note that the 8-bit offset held in pca0cph5 is compared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the value of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 25.4 , where pca0l is the value of the pca0l register at the time of the update. equation 25.4. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflows while there is a match between pca0cph5 and pca0h. software may force a wdt reset by writing a ?1? to the ccf5 flag (pca0cn.5) while the wdt is enabled. 25.3.2. watchdog timer usage to configure the wdt, perform the following tasks: disable the wdt by writing a ?0? to the wdte bit. select the desired pca clock source (with the cps2-cps0 bits). load pca0cpl5 with the desired wdt update offset value. configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). enable the wdt by setting the wdte bit to ?1?. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any reset. the pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl5 defaults to 0x00. using equation 25.4 , this results in a wdt timeout interval of 3072 system clock cycles. ta b le 25.3 lists some example timeout intervals for typical system clocks. offset 256 pca 0 cpl 5 () 256 pca 0 l ? () + =
C8051F410/1/2/3 260 rev. 0.8 table 25.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl5 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 18,432,000 255 42.7 18,432,000 128 21.5 18,432,000 32 5.5 11,059,200 255 71.1 11,059,200 128 35.8 11,059,200 32 9.2 3,062,500 255 257 3,062,500 128 129.5 3,062,500 32 33.1 191,406 2 255 4109 191,406 2 128 2070 191,406 2 32 530 32,000 255 24576 32,000 128 12384 32,000 32 3168 notes: 1. assumes sysclk / 12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal oscillator reset frequency.
rev. 0.8 261 C8051F410/1/2/3 25.4. register descriptions for pca following are detailed descriptions of the special function registers related to the operation of the pca. sfr definition 25.1. pca0cn: pca control bit7: cf: pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. bit0: ccf5: pca module 5 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf5 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit4: ccf4: pca module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf4 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit3: ccf3: pca module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf3 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit2: ccf2: pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit1: ccf1: pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit0: ccf0: pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xd8
C8051F410/1/2/3 262 rev. 0.8 sfr definition 25.2. pca0md: pca mode bit7: cidl: pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while the system controller is in idle mode. bit6: wdte: watchdog timer enable if this bit is set, pca module 5 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 5 enabled as watchdog timer. bit5: wdlck: watchdog timer lock this bit locks/unlocks the watchdog timer enable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. bit4: unused. read = 0b, write = don't care. bits3?1: cps2?cps0: pca counter/timer pulse select. these bits select the timebase source for the pca counter . bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca counter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. r/w r/w r/w r r/w r/w r/w r/w reset value cidl wdte wdlck - cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 101 external clock divided by 8 * 110 smartclock clock divided by 8 * 111reserved *note: external clock divided by 8 and smartclock clock divided by 8 are synchronized with the system clock.
rev. 0.8 263 C8051F410/1/2/3 sfr definition 25.3. pca0cpmn: pca capture/compare mode bit7: pwm16n: 16-bit pulse width modulation enable. this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the comparator function for pca module n. 0: disabled. 1: enabled. bit5: cappn: capture positive function enable. this bit enables/disables the positive edge capture for pca module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca module n. when enabled, matches of the pca counter with a module's capture/compare register cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca module n. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn matn togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cpm0: 0xda, pca0cpm1: 0xdb, pca0cpm2: 0xdc, pca0cpm3: 0xdd, pca0cpm4: 0xde, pca0cpm5: 0xce
C8051F410/1/2/3 264 rev. 0.8 sfr definition 25.4. pca0l: pca counter/timer low byte sfr definition 25.5. pca0h: pca counter/timer high byte sfr definition 25.6. pca0cpln: pca capt ure module low byte sfr definition 25.7. pca0cphn: pca capture module high byte bits 7?0: pca0l: pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf9 bits 7?0: pca0h: pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: 0xfa bits7?0: pca0cpln: pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cpl0: 0xfb, pca0cpl1: 0xe9, pca0cpl2: 0xeb, pca0cpl3: 0xed, pca0cpl4: 0xfd, pca0cpl5: 0xd2 bits7?0: pca0cphn: pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cph0: 0xfc, pca0cph1: 0xea, pca0cph2: 0xec, pca0cph3: 0xee, pca0cph4: 0xfe, pca0cph5: 0xd3
rev. 0.8 265 C8051F410/1/2/3 26. c2 interface c8051f41x devices include an on-chip silicon laboratories 2-wire (c2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interface specification for details on the c2 protocol. 26.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec - ification. c2 register definition 26.1. c2add: c2 address c2 register definition 26.2. deviceid: c2 device id bits7-0: the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id register for data read instructions (deviceid) 0x01 selects the revision id register for data read instructions (revid) 0x02 selects the c2 flash programming control register for data read/write instructions (fpctl) 0xb4 selects the c2 flash programming data register for data read/write instructions (fpdat) this read-only register returns the 8-bit device id: 0x0c (c8051f41x). reset value 00001011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
C8051F410/1/2/3 266 rev. 0.8 c2 register definition 26.3. revid: c2 revision id c2 register definition 26.4. fpctl: c2 flash programming control c2 register definition 26.5. fpdat: c2 flash programming data this read-only register returns the 8-bit revision id: 0x00 (revision a). reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bits7-0 fpctl: flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset must be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bits7-0: fpdat: c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
rev. 0.8 267 C8051F410/1/2/3 26.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared with user functions so that in-system debugging and flash programming functions may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?borrow? the c2ck (/rst) and c2d (p2.7) pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typi - cal isolation configuration is shown in figure 26.1 . figure 26.1. typical c2 pin sharing the configuration in figure 26.1 assumes the following: 1. the user input (b) cannot change state while the target device is halted. 2. the /rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx
C8051F410/1/2/3 268 rev. 0.8 d ocument c hange l ist revision 0.7 to revision 0.8 updated specification tables with most recently available characterization data. corrected references to configuring pins fo r analog mode - port latch must contain a '1'. sfr definition 5.6 : address correction to 0xba. added figure 8.2 showing power connection diagram without using on-chip regulator. section 9 : removed references to "high speed analog mode". table 11.2 : corrected sfr name p2mdin on location 0xf3. section 14 : corrected operational description of crc engine. section 18 , important note on page 151 : added "and have the same behavior as p0 in normal mode." to last sentence. section 19.2.2 : inserted step 3 "release the crystal pins by writing ?1's to the port latch." section 19.3 : added figure 19.3 and text to describe behavior of clock multiplier with slower input fre - quencies. section 21 : corrected smbus maximum rate to 1/20th system clock. table 21.4 : made corrections to smbus state descriptions. figure 24.6 : corrected t2rclk mux selection options. figure 24.9 : corrected t3rclk mux selection options. c2 register definition 26.2 : corrected deviceid value to 0x0c.
rev. 0.8 269 C8051F410/1/2/3 n otes :
C8051F410/1/2/3 270 rev. 0.8 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: mcuinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames m entioned herein are trademarks or register ed trademarks of their respective holders the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequen ces resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories re serves the right to make changes without further notice. sili con laboratories makes no warranty, representation or guarantee regar ding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liability arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incidental damages. silicon laboratories product s are not designed, intended, or authorized for use in applications intended to support or su stain life, or for any other application in which the failure of the silicon laboratories produc t could create a situation where personal injury or death may occur. should buyer purchase or use silicon laborator ies products for any such unintended or unauthor ized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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